Gate Delay Estimation in STA under Dynamic Power Supply Noise

Okumura, Takaaki; Minami, Fumihiro; Shimazaki, Kunihiko; Kuwada, Kimihiko; Hashimoto, Masanori

doi:10.1587/transfun.e93.a.2447

Cited by 15 publications

(8 citation statements)

References 8 publications

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“…It is rather the combined effect across all the instances in these paths. But since spatial variation in voltage drops can be signif icant it is not sufficient to integrate the voltage deviation across the clock cycle and study only the average IR drop's timing implication as argued in [7] for 180 nm. For hold timing rela tionships on the other hand, it is the difference of two almost equally long (mostly clock) paths that is of interest, and thus it is the sharp and large peaks of Fig.…”

Section: Analysis Of Results Inmentioning

confidence: 99%

Extracting vectors from application traces for power integrity analysis

Olsson

Pihl

Andersson

et al. 2011

2011 IEEE 15th Workshop on Signal Propagation on Interconnects (SPI)

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We present an approach to power integrity analysis that is based on traces resulting from application execution. The first phase of the approach identifies a vector that maximally stresses the power grid, while the second phase entails simulation of the selected vector on an accurate grid model. We show, for an AV R32 32-bit microcontroller, that the vector we identify gives rise to a supply voltage drop that is 18% larger than that of the vector obtained in a regular flow, which considers average power dissipation per cycle.

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Section: Analysis Of Results Inmentioning

confidence: 99%

Extracting vectors from application traces for power integrity analysis

Olsson

Pihl

Andersson

et al. 2011

2011 IEEE 15th Workshop on Signal Propagation on Interconnects (SPI)

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“…This method still does not capture the 'true' dynamic behavior of the supply noise waveform. To assess the impact of supply voltage noise on circuit performance, [15] suggests that using average supply voltage, rather than dynamic behavior, can be well-correlated with measurements; however, the authors fail to demonstrate the limitations of timing analysis using static IR-drop analysis as noted in [14].…”

Section: Related Workmentioning

confidence: 99%

“…Recently, Okumura et al [14] have proposed a gate delay calculation approach which considers the dynamic behavior of the supply voltage noise by considering noise waveform slew and magnitude. However, in their characterization setup they do not allow all the relevant parameters (i.e., input slew, noise slew, noise magnitude, etc.)…”

Section: Related Workmentioning

confidence: 99%

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Worst-case performance prediction under supply voltage and temperature variation

Cheng

Kahng

Samadi

et al. 2010

Proceedings of the 12th ACM/IEEE International Workshop on System Level Interconnect Prediction

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The power delivery network (PDN) is a major consumer of interconnect resources in deep-submicron designs (i.e., more than 30% of the entire routing area) [18]. Hence, efficient early-stage PDN optimization enables the designers to ensure a desired power-performance envelope. On the other hand as technology scales, gate delays become more sensitive to power supply variation. In addition, emerging 3D designs are more prone to supply voltage and temperature variation due to increased power density. In this paper, we develop accurate inverter cell delay and output slew models under supply voltage and temperature variation. Our models are within 6% of SPICE simulations on average. We use our single-cell delay and output slew models to estimate the delay of a path (i.e., an inverter chain, etc.). We also present a methodology to find the worst-case input configuration (i.e., input slew, output load, cell size, noise magnitude, noise slew, noise offset and temperature) that causes the delay of the given path is maximized. We believe that our models can efficiently drive accurate worst-case performance-driven PDN optimization.

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“…For example, signal propagation delay, on the ATE device power supply (DPS) and on a practical customer power supply indicate disparate properties [12][13][14], and considerable problems arise. In the case where an ATE DPS is worse than the customer power supply, since the signal propagation delays of the DUTs increase on the ATE, such an at-speed functional test on the ATE may say BFail^for some devices even though they operate correctly under the customer environment.…”

Section: Introductionmentioning

confidence: 99%

Dynamic Power Integrity Control of ATE for Eliminating Overkills and Underkills in Device Testing

et al. 2016

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This paper proposes a power integrity control technique for dynamically controlling power supply voltage fluctuations for a device under test (DUT), and demonstrates its effectiveness for eliminating the overkills/underkills due to the difference of power supply impedance between an automatic test equipment (ATE) and a practical operating environment of the DUT. The proposed method injects compensation currents into the power supply nodes on the ATE system in a feedforward manner such that the ATE power supply waveform matches with the one on the customer's operating environment of the DUT. A method for calculating the compensation current is also described. Experimental results show that the proposed method can emulate the power supply voltage waveform under a customer's operating condition and eliminate 95 % of overkills/underkills in the maximum operating frequency testing with 105 real silicon devices. Limitations and applications of the proposed method are also discussed.

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Gate Delay Estimation in STA under Dynamic Power Supply Noise

Cited by 15 publications

References 8 publications

Extracting vectors from application traces for power integrity analysis

Extracting vectors from application traces for power integrity analysis

Worst-case performance prediction under supply voltage and temperature variation

Dynamic Power Integrity Control of ATE for Eliminating Overkills and Underkills in Device Testing

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