This paper and its companion (Part I) are devoted to to the analysis of the application of a chaotic piecewise-linear one-dimensional (PL1D) map as Random Number Generator (RNG). In Part I, we have mathematically analyzed the information generation process of a class of PL1D maps. In this paper, we find optimum parameters that give an RNG with lowest redundancy and maximum margin against parasitic attractors. Further, the map is implemented in a 0.8 m standard CMOS process utilizing switched current techniques. Post-layout circuit simulations of the RNG indicate no periodic attractors over variations in temperature, power supply and process conditions, and maximum redundancy of 0.4%. We esimate that the output bit rate of our RNG is 1 Mbit/s, which is substantially higher than the output bit rate of RNGs available on the market.

A generator for multiplier and squarer structures, suitable for high performance bit-parallel DSP applications in VLSI, is presented. The squarer structure employs a novel bit-parallel partial product reduction scheme, reducing delay and hardware by 50%, compared to a full multiplication. The generator is based on optimized Wallace trees, Booth encoding and binary tree vector merging addition. Computation of weighted square sums is used as a design example, which has applications in e.g. pattern recognition. Results indicate a delay reduction of 10-20% compared to traditional designs for high speed, as well as a reduction in power and area, for a standard 0 . 8~ CMOS process.

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