A multiplier and squarer generator for high performance DSP applications

Abstract

A generator for multiplier and squarer structures, suitable for high performance bit-parallel DSP applications in VLSI, is presented. The squarer structure employs a novel bit-parallel partial product reduction scheme, reducing delay and hardware by 50%, compared to a full multiplication. The generator is based on optimized Wallace trees, Booth encoding and binary tree vector merging addition. Computation of weighted square sums is used as a design example, which has applications in e.g. pattern recognition. Results indicate a delay reduction of 10-20% compared to traditional designs for high speed, as well as a reduction in power and area, for a standard 0 . 8~ CMOS process.

Efficient unsigned squarer design techniques

“…The folding technique described in [1] uses the symmetry of the partial product matrix (PPM) of squarer to archive 50% reduction of the number of partial products compared with a standard multiplier. The partial products rearrangement technique in [2,3] is used to reduce the total number of partial product bits and the depth of PPM.…”

Fast‐squarer circuits using 3‐bit‐scan without overlapping bits

“…When realized using the STMicroelectronics (ST) 90 nm 1V CMOS standard cells library, the multiplier is ∼ 20% slower, consumes ∼ 70% more power and occupies ∼ 70% more silicon area. For this reason several efficient techniques have been proposed in the past for both ASIC [8][9][10][11][12][13][14][15] and FPGA-based [16] implementations of squaring circuits.…”

A Low Power High Performance Radix-4 Approximate Squaring Circuit

“…Approximate squaring circuits have numerous applications as mentioned in [12][13][14][15]20] such as cryptography, computation of Euclidean distance among pixels for a graphics processor or in rectangular to polar conversions in several signal processing circuits where full precision results are not required. As indicated in [14,25], customized squaring modules do have important applications in digital signal processing.…”

“…As indicated in [14,25], customized squaring modules do have important applications in digital signal processing. Specifically, in [6], a method is described where resolution can be increased during a graphics blend operation through the incorporation of a squaring operation implemented by a multiplier followed by a truncation circuit.…”

“…This property has been investigated to provide optimizations in multiplier design at the bit level [18,19]. The design focusing on a squaring circuit employing this symmetry was proposed in [21], and numerous studies optimizing binary squaring circuits appear in [12][13][14][15]20]. These designs primarily optimize by using hardwired bit product arrangements to reduce array sizes for efficient accumulation, mostly focusing on low precision.…”