A generator for multiplier and squarer structures, suitable for high performance bit-parallel DSP applications in VLSI, is presented. The squarer structure employs a novel bit-parallel partial product reduction scheme, reducing delay and hardware by 50%, compared to a full multiplication. The generator is based on optimized Wallace trees, Booth encoding and binary tree vector merging addition. Computation of weighted square sums is used as a design example, which has applications in e.g. pattern recognition. Results indicate a delay reduction of 10-20% compared to traditional designs for high speed, as well as a reduction in power and area, for a standard 0 . 8~ CMOS process.

No abstract

No abstract

A design process model with focus on design quality is presented. Design quality is quantified as the probability that a design object satisjies its specification. Simple economic models demonstrate how design quality may impact cost, revenue, and lead time. Finally, design experiments done by several students are reported to exemplify the collection of design process parameters. These experiments also demonstrate the applicability of such parameters and quality models to real-life design projects.

For data dominated applications, the system level design trajectory should first focus on finding a good data transfer and storage solution. Since no realization details are available at this level, estimates are needed to guide the designer. This paper presents an algorithm for automated estimation of strict upper and lower bounds on the individual data dependency sizes in high level application code given a partially fmed execution ordering. Previous work has either not taken execution ordering into account at all, resulting in large overestimates, or required a fully specified ordering which is usually not available at this high level. The usefulness of the methodology is illustrated on representative application demonstrators.