Abstract-This paper discusses how to cope with dynamic power supply noise in FF timing estimation. We first review the dependence of setup and hold time on supply voltage, and point out that setup time is more sensitive to supply voltage than hold time and hold time at nominal voltage is reasonably pessimistic. We thus propose a procedure to estimate setup time and clock-to-Q delay taking into account given voltage drop waveforms using an equivalent DC voltage approach. Experimental results show that the proposed procedure estimates setup time and clock-to-Q delay fluctuations well with 5% and 3% errors on average. I. INTRIDUCTIONRecently, Power/Ground voltage level fluctuation (PG noise) is becoming a primary concern in designing LSI products with the progress of technology scaling. Current density in a chip has been increasing due to increase in operating frequency and power consumption. Moreover, lowering supply voltage with technology scaling, over-drive voltage (V dd -V th ) is decreasing, which results in higher sensitivity of gate delay to power supply voltage [1]. On the other hand, [2] predicts that PG noise level is nearly constant despite lowering power supply voltage. These tendencies make circuit timing more susceptible to supply noise, and hence timing verification taking PG noise into account is essential for successful chip design.Several gate delay estimation methods considering a given noise waveform have been proposed to capture the impact of dynamic noise behavior on timing [7] experimentally compares the variations between combinational circuit delay and setup/hold times under constant voltage drop, and pointed out a cancellation behavior. However, to the best of our knowledge, the variation of setup and hold times and clock-to-Q delay under dynamic voltage drop has not been discussed so far.In this paper, we discuss how to estimate setup and hold times and clock-to-Q delay under given dynamic voltage drop. We first investigate their tendencies under dynamic voltage drop and show that the setup time becomes optimistic while the hold time constraint becomes pessimistic under the noise. We then propose an estimation procedure of the setup time and clock-to-Q delay under the dynamic noise on the basis of [1], and evaluate the estimation accuracy.

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Leakage current is an important qualitative metric of LSI (Large Scale Integrated circuit). In this paper, we focus on reduction of leakage current variation under the process variation. Firstly, we derive a set of quadratic equations to evaluate delay and leakage current under the process variation. Using these equations, we discuss the cases of varying leakage current without degrading delay distribution and propose a procedure to reduce the leakage current variations. From the experiments, we show the proposed method effectively reduces the leakage current variation up to 50% at 90 percentile point of the distribution compared with the conventional design approach.

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