An Approach for Reducing Leakage Current Variation due to Manufacturing Variability

Abstract

Leakage current is an important qualitative metric of LSI (Large Scale Integrated circuit). In this paper, we focus on reduction of leakage current variation under the process variation. Firstly, we derive a set of quadratic equations to evaluate delay and leakage current under the process variation. Using these equations, we discuss the cases of varying leakage current without degrading delay distribution and propose a procedure to reduce the leakage current variations. From the experiments, we show the proposed method effectively reduces the leakage current variation up to 50% at 90 percentile point of the distribution compared with the conventional design approach.

A novel constant-g_m rail-to-rail input stage for operational amplifiers

“…(3) However, this square root 1: 3 current mirror is based on the square characteristic of MOS transistor drain current and the channel length modulation of the transistor is ignored. In modern deep sub-micron CMOS technology, the drain current of MOS transistor in the saturated region no longer accurately follows the square law [10]- [17], which is the serious defect of this structure. Another method [18]- [24] is to regulate the gm by keeping the sum of the gate source voltage of the PMOS and the NMOS differential pair constant.…”