Gate drive circuit for current balancing of parallel-connected SiC-JFETs under avalanche mode

Takamori, Taro; Wãda, Keiji; Saito, Wataru; Nishizawa, Shin Ichi

doi:10.1016/j.microrel.2020.113776

Cited by 10 publications

(3 citation statements)

References 7 publications

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“…However, in the case of the parallel connection configuration, a current imbalance issue occurs in power semiconductor devices. The phenomenon is caused by the breakdown voltage characteristics of paralleled power devices [24]- [26]. Such operations create high thermal conditions biased toward devices with lower breakdown voltage characteristics.…”

Section: Introductionmentioning

confidence: 99%

Paralleled SiC MOSFETs Circuit Breaker With a SiC MPS Diode for Avalanche Voltage Clamping

Takamori,

Wada,

Saito

et al. 2024

IEEE Open J. Power Electron.

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This paper proposes a solid-state circuit breaker comprising silicon carbide (SiC) MOSFETs and a SiC diode, based on the principle of avalanche voltage clamping. The key challenge in realizing a solid-state circuit breaker lies in reducing conduction loss. A parallel connection of power semiconductor devices is the suitable configuration that can meet these requirements. However, in such a configuration, the current balance during cutoff operation may be affected by the variation in the breakdown voltage characteristics of the power semiconductor devices. To address this issue, the proposed circuit breaker employs clamping with a SiC merged pin-Schottky (MPS) diode, with high avalanche tolerance and robust characteristics under repetitive avalanche events. The effectiveness of the proposed solid-state circuit breaker is validated through experiments conducted in an unclamped inductive switching (UIS) test circuit using a 400-V, 50-A DC distribution system. Eventually, the demonstrations indicate that the SiC diode clamping method contributes to more compact implementations for solid-state circuit breakers.

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Section: Introductionmentioning

confidence: 99%

Paralleled SiC MOSFETs Circuit Breaker With a SiC MPS Diode for Avalanche Voltage Clamping

Takamori,

Wada,

Saito

et al. 2024

IEEE Open J. Power Electron.

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“…T HE development of solid-state circuit breakers for power electronic DC applications has seen a variety of different approaches [1]- [5]. Recent investigations of circuit breakers employing normally-on SiC JFETs revealed excellent results in terms of current handling capability and turn-off speed [6]- [8]. Moreover, a self-powered two-port circuit breaker architecture was proposed allowing for placement directly in a circuit branch [9]- [11].…”

Section: Introductionmentioning

confidence: 99%

A Monolithically Integrated SiC Circuit Breaker

Boettcher

Erlbacher

2021

IEEE Electron Device Lett.

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In this letter, a monolithically integrated SiC circuit breaker device providing self-triggered blocking operation is presented. The proposed topology is implemented into a common 4H-SiC JFET technology, which offers conventional cell design and chip scaling opportunities. Basic operation and design implications are discussed on the basis of quasi-static electrical measurements of fabricated nJFET, pJFET and circuit breaker devices. The design of experiment including a variation of channel length and channel doping dose reveals a distinct effect on the design targets, especially on on-state resistance, trigger current and blocking voltage. The investigated devices exhibit trigger current density levels of up to 2.8 A/cm² and self-sustained blocking capability up to 795 V DC-link voltage. On-state resistance at room temperature is determined to 0.93 Ωcm² but drastically decreases at elevated temperatures, as is shown in the experiments.

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“…[1][2][3] In particular, junction field-effect transistors (JFETs) have been widely used in silicon-based high voltage integrated circuits (ICs) because of their high input impedance, low noise, small power consumption, good process compatibility, and temperature performance. [4][5][6][7] Various techniques and methods such as the long field plate, N-type drift and design of the reversed PN junction location, have been used to increase the breakdown voltage of the conventional JFETs.…”

Section: Introductionmentioning

confidence: 99%

Design and investigation of novel ultra-high-voltage junction field-effect transistor embedded with NPN*

Feng

et al. 2021

Chinese Phys. B

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Ultra-high-voltage (UHV) junction field-effect transistors (JFETs) embedded separately with the lateral NPN (JFET-LNPN), and the lateral and vertical NPN (JFET-LVNPN), are demonstrated experimentally for improving the electrostatic discharge (ESD) robustness. The ESD characteristics show that both JFET-LNPN and JFET-LVNPN can pass the 5.5-kV human body model (HBM) test. The JFETs embedded with different NPNs have 3.75 times stronger in ESD robustness than the conventional JFET. The failure analysis of the devices is performed with scanning electron microscopy, and the obtained delayer images illustrate that the JFETs embedded with NPN transistors have good voltage endurance capabilities. Finally, the internal physical mechanism of the JFETs embedded with different NPNs is investigated with emission microscopy and Sentaurus simulation, and the results confirm that the JFET-LVNPN has stronger ESD robustness than the JFET-LNPN, because the vertical NPN has a better electron collecting capacity. The JFET-LVNPN is helpful in providing a strong ESD protection and functions for a power device.

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Gate drive circuit for current balancing of parallel-connected SiC-JFETs under avalanche mode

Cited by 10 publications

References 7 publications

Paralleled SiC MOSFETs Circuit Breaker With a SiC MPS Diode for Avalanche Voltage Clamping

Paralleled SiC MOSFETs Circuit Breaker With a SiC MPS Diode for Avalanche Voltage Clamping

A Monolithically Integrated SiC Circuit Breaker

Design and investigation of novel ultra-high-voltage junction field-effect transistor embedded with NPN*

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