Gate engineered heterostructure junctionless TFET with Gaussian doping profile for ambipolar suppression and electrical performance improvement

Aghandeh, Hadi; Ziabari, Seyed Ali Sedigh

doi:10.1016/j.spmi.2017.06.018

Cited by 53 publications

(24 citation statements)

References 44 publications

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“…Electronics 2019, 8, x FOR PEER REVIEW 2 of 10 the operating voltage. Therefore, TFETs would be one of the most promising alternatives to MOSFET in low-power integrated circuit applications [11,12]. However, there are also inherent disadvantages in TFETs, such as the small on-state current and large miller capacitance [13].…”

Section: Methodsmentioning

confidence: 99%

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Design and Investigation of the Junction-Less TFET with Ge/Si0.3Ge0.7/Si Heterojunction and Heterogeneous Gate Dielectric

et al. 2019

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To improve the on-state current and reduce the miller capacitance of the conventional junction-less tunneling field effect transistor (JLTFET), the junction-less TFET with Ge/Si0.3Ge0.7/Si heterojunction and heterogeneous gate dielectric (H-JLTFET) is investigated by the Technology Computer Aided Design (TCAD) simulation in this paper. The source region uses the narrow bandgap semiconductor material germanium to obtain the higher on-state current; the gate dielectric adjacent to the drain region adopts the low-k dielectric material SiO2, which is considered to reduce the gate-to-drain capacitance effectively. Moreover, the gap region uses the Si0.3Ge0.7 material to decrease the tunneling distance. In addition, the effects of the device sizes, doping concentration and work function on the performance of the H-JLTFET are analyzed systematically. The optimal on-state current and switching ratio of the H-JLTFET can reach 6 µA/µm and 2.6 × 1012, which are one order of magnitude and four orders of magnitude larger than the conventional JLTFET, respectively. Meanwhile, the gate-to-drain capacitance, off-state current and power consumption of the H-JLTFET can be effectively suppressed, so it will have a great potential in future ultra-low power integrated circuit applications.

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Section: Methodsmentioning

confidence: 99%

“…Besides, TFETs can also decrease the operating 2 of 10 voltage. Therefore, TFETs would be one of the most promising alternatives to MOSFET in low-power integrated circuit applications [11,12].…”

Section: Introductionmentioning

confidence: 99%

Design and Investigation of the Junction-Less TFET with Ge/Si0.3Ge0.7/Si Heterojunction and Heterogeneous Gate Dielectric

et al. 2019

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“…To avoid complex fabrication processes and high thermal budgets in TFETs, the junctionless tunneling field effect transistor (JLTFET) [22][23][24][25][26][27][28][29][30] has been studied extensively in recent years, which uses uniformly high-doping concentration in the source, channel and drain regions so that the doping concentration and type of channel region are consistent with source region and drain region. Due to uniform doping, the JLTFET is immune to random dopant fluctuations (RDFs) and overcomes complex fabrication processes in manufacturing, meanwhile, source and drain region are formed by the charge plasma concept which further avoids high thermal budgets in the JLTFET.…”

Section: Introductionmentioning

confidence: 99%

Design and Investigation of a Dual Material Gate Arsenic Alloy Heterostructure Junctionless TFET with a Lightly Doped Source

et al. 2019

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This paper designs and investigates a novel structure of dual material gate-engineered heterostructure junctionless tunnel field-effect transistor (DMGE-HJLTFET) with a lightly doped source. Similar to the conventional HJLTFET, the proposed structure still adopts an InAs/GaAs0.1Sb0.9 heterojunction at source and channel interface and employs a polarization electric field at the arsenic heterojunction induced by the lattice mismatch in the InAs and GaAs0.1Sb0.9 zinc blende crystal to improve band to band tunneling (BTBT) current. However, the gate electrode is divided into three parts in DMGE-HJLTFET namely the auxiliary gate (M1), control gate (M2) and tunnel gate (M3) with workfunctions ΦM1, ΦM2 and ΦM3, where ΦM1 = ΦM3 < ΦM2, which not only improves ON-state current but also decreases the OFF-state current. In addition, a lightly doped source is used to further decrease the OFF-state current of this device. Simulation results indicate that DMGE-HJLTFET provides superior metrics in terms of logic and analog/radio frequency (RF) performance as compared with conventional HJLTFET, the maximum ON-state current and transconductance of the DMGE-HJLTFET increases up to 5.46 × 10−4 A/μm and 1.51 × 10−3 S/μm at 1.0 V drain-to-source voltage (Vds). Moreover, average subthreshold swing (SSave) of DMGE-HJLTFET is as low as 15.4 mV/Dec at low drain voltages. Also, DMGE-HJLTFET could achieve a maximum cut-off frequency (fT) of 423 GHz at 0.92 V gate-to-source voltage (Vgs) and a maximum gain bandwidth (GBW) of 82 GHz at Vgs = 0.88 V, respectively. Therefore, it has great potential in future ultra-low power integrated circuit applications.

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“…To avoid the above issues in TFETs, the junctionless tunneling field effect transistor (JLTFET) [24][25][26][27][28][29][30] is proposed, which uses a uniformly high-doping concentration in source, channel, and drain region, wherein the doping concentration and type of channel are consistent with source and drain. Therefore, junctionless tunnel field-effect transistor (JLTFET) is immune to random dopant fluctuations (RDFs) [31], while complex fabrication processes and high thermal budgets in JLTFET manufacturing can be effectively avoided by the charge plasma concept.…”

Section: Introductionmentioning

confidence: 99%

Improvement of Electrical Performance in Heterostructure Junctionless TFET Based on Dual Material Gate

et al. 2019

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In this paper, a dual metallic material gate heterostructure junctionless tunnel field-effect transistor (DMMG-HJLTFET) is proposed and investigated. We use the Si/SiGe heterostructure at the source/channel interface to improve the band to band tunneling (BTBT) rate, and introduce a sandwich stack (GaAs/Si/GaAs) at the drain region to suppress the OFF-state current and ambiplolar current. Simultaneously, to further decrease ambipolar current, the gate electrode is divided into three parts namely auxiliary gate (M1), control gate (M2), and tunnel gate (M3) with workfunctions Φ M1 , Φ M2 and Φ M3 , respectively, where Φ M1 = Φ M3 < Φ M2 . Simulation results indicate that DMMG-HJLTFET provides superior performance in terms of logic and analog/RF as compared with other possible combinations, the ON-state current of the DMMG-HJLTFET increases up to 9.04 × 10 −6 A/µm, and the maximum g m (which determine the analog performance of devices) of DMMG-HJLTFET is 1.11 × 10 −5 S/µm at 1.0V drain-to-source voltage (Vds). Meanwhile, RF performance of devices depends on the cut-off frequency (f T ) and gain bandwidth (GBW), and DMMG-HJLTFET could achieve a maximum f T of 5.84 GHz, and a maximum GBW of 0.39 GHz, respectively.

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Gate engineered heterostructure junctionless TFET with Gaussian doping profile for ambipolar suppression and electrical performance improvement

Cited by 53 publications

References 44 publications

Design and Investigation of the Junction-Less TFET with Ge/Si0.3Ge0.7/Si Heterojunction and Heterogeneous Gate Dielectric

Design and Investigation of the Junction-Less TFET with Ge/Si0.3Ge0.7/Si Heterojunction and Heterogeneous Gate Dielectric

Design and Investigation of a Dual Material Gate Arsenic Alloy Heterostructure Junctionless TFET with a Lightly Doped Source

Improvement of Electrical Performance in Heterostructure Junctionless TFET Based on Dual Material Gate

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