Gate engineering for deep-submicron CMOS transistors

Abstract

Gate depletion and boron penetration through thin gate oxide place directly opposing requirements on the gate engineering for advanced MOSFET's. In this paper, several important issues of deep-submicron CMOS transistor gate engineering are discussed. First, the impact of gate nitrogen implantation on the performance and reliability of deep-submicron CMOSFET's is investigated. The suppression of boron penetration is confirmed by the SIMS profiles, and is attributed mainly to the diffusion retardation effect in bulk polysilicon by the presence of nitrogen. The MOSFET I0V characteristics, MOS capacitor quasi-static C0V curves, SIMS profiles, gate sheet resistance, and oxide Q bd are compared for different nitrogen implant conditions. A nitrogen dose of 5 2 10 15 cm 02 is found to be the optimum choice at an implant energy of 40 KeV in terms of the overall electrical behavior of CMOSFET's. Under optimum design, gate nitrogen implantation is found to be effective in eliminating boron penetration without degrading performance of either p + gate p-MOSFET and n + gate n-MOSFET. Secondly, the impact of gate microstructure on the performance of deep-submicron CMOSFET's is discussed by comparing poly and amorphous silicon gate deposition technologies. Thirdly, poly-Si 10x Ge x is presented as a superior alternative gate material. Higher dopant activation efficiently results in higher active dopant concentration near the gate/SiO 2 interface without increasing the gross dopant concentration. This plus the lower annealing temperature suppress the dopant penetration. Phosphorus-implanted poly-Si 0:8 Ge 0:2 gate is compared with polysilicon gate in this study.

DC Improvements and Low-Frequency 1/f Noise Characteristics of Complimentary Metal–Oxide–Semiconductor Transistors with a Single n+-Doped Polycrystalline Si/SiGe Gate Stack

“…The effect of gate depletion on transistor current drive is estimated using the inversion charge Q inv . As observed by Yu et al 4) in SiGe and poly-Si gate capacitors, the ratio (Q inv SiGe =Q inv Si ) is greater than unity and increases as (V GS À V T ) increases. As shown in Figs.…”

“…The achieved reduction in the extent of gate depletion and the improved DC characteristics agree with results reported in the literature. 4,5) Note that, in a previous study, a single p þ -doped, poly-Si 1Àx Ge x gate material was used to solve problems with B-penetration. 6) Also note that, as the gate oxide layer becomes thinner, the benefit of using SiGe gates becomes clearer.…”

Single-crystalline silicon nanomembrane thin-film transistors with anodized aluminum oxide as a gate dielectric on rigid and flexible substrates

“…This phenomenon was mainly attributed to the influence of the roughness of the substrates. When the AAO was formed, the rough substrate induced more defects in the AAO compared with the dielectric layer fabricated on a smooth substrate [38][39][40], which affected the gate dielectric capacitance and thus caused performance degradation of the TFTs [41,42]. In addition, the electrode stacked on the dielectric layer could have larger roughness, thus the electric field distribution and surface charge density were affected, leading to the degradation of the effective unit-area capacitance of the dielectric layer [43,44].…”

Development of highly reliable static random access memory for 40-nm embedded split gate-MONOS flash memory

“…To suppress the gate depletion, additional gate annealing and a thin poly-Si film were applied. [20][21][22][23] Excessive gate annealing and thinner gate poly-Si film resulted in gate impurity inter-diffusion and gate impurity leakage to the MOS channel. Therefore, optimization of the annealing conditions and film thickness is needed.…”