Gate-Induced Threshold Voltage Instabilities in p-Gate GaN HEMTs

Evaluation on Temperature-Dependent Transient VT Instability in p-GaN Gate HEMTs under Negative Gate Stress by Fast Sweeping Characterization

“…The behavior of Δ V T could be linked to three physical processes, as illustrated in Figure 8 a,b: Donor-type hole trap states at the p-GaN/AlGaN interface could be activated and release holes to the valence band in the p-GaN layer [ 17 , 18 ]; The depletion width of SCR, in the p-GaN layer of SG HEMTs, would decrease under the negative gate bias stress, which also leads to hole release [ 4 ]; Holes could flow from the gate-source drift region, towards the gate stack, and under large negative gate bias stress. Part of the holes may flow out to the gate terminal and contribute to the gate current, while part of the holes may get trapped into the gate stack region and lead to an extra hole accumulation [ 16 ]. …”

“…Holes could flow from the gate-source drift region, towards the gate stack, and under large negative gate bias stress. Part of the holes may flow out to the gate terminal and contribute to the gate current, while part of the holes may get trapped into the gate stack region and lead to an extra hole accumulation [ 16 ].…”

“…The gate bias stress-induced threshold voltage ( V T ) instability of p-GaN gate HEMTs has been widely investigated recently, and the imbalanced extra charge accumulation, caused by the (de-) trapping of holes or electrons in the gate stack region, has been proposed as the main physical cause [ 6 , 7 , 8 , 9 , 10 , 11 , 12 , 13 , 14 , 15 , 16 , 17 , 18 , 19 ]. Considering that normally-off p-GaN gate devices feature a relatively low V T voltage, applying negative gate voltage is an important method for improving the dv/dt robustness and preventing possible false turning-on induced by system noise [ 20 , 21 , 22 ].…”

“…Considering that normally-off p-GaN gate devices feature a relatively low V T voltage, applying negative gate voltage is an important method for improving the dv/dt robustness and preventing possible false turning-on induced by system noise [ 20 , 21 , 22 ]. Nevertheless, most studies have focused on the impacts of positive gate bias stress [ 6 , 7 , 8 , 9 , 10 , 11 , 12 , 13 , 14 , 15 ], but less attention has been given to the impact of negative gate bias stress on device V T instability [ 4 , 16 , 17 , 18 ]. Elangovan et al recently analyzed the instability behavior of Schottky-type E-mode p-GaN gate power HEMTs through pulsed negative gate bias stress tests and attributed the positive threshold shift (Δ V T ) to the hole deficiency in the p-GaN region [ 17 ].…”

Unipolar and Bipolar Pulsed Gate Stresses and Threshold Voltage Shifts in GaN e-HEMTs

“…This figure shows that when the gate of the device is subjected to a positive voltage, electron injection into the p-GaN layer and hole injection into the AlGaN layer can occur with opposing effects on threshold voltage shifting. This means both positive and negative charge trapping can occur at the different interfaces of the complicated multi-layer GaN structure [5][6][7][8][9][10][11]. In [12], positive VGS stress resulted in positive VTH shift when the VTH measurement was performed 50 µs after stress removal.…”