Gate length scaling beyond Si: Mono-layer 2D Channel FETs Robust to Short Channel Effects

Dorow, C. J.; Penumatcha, Ashish V.; Kitamura, A.; Rogan, C.; O’Brien, Kevin; Lee, S.; Ramamurthy, R.; Cheng, C. -Y.; Maxey, K.; Zhong, Tao; Tronic, Tristan A.; Holybee, B.; Richards, John F.; Oni, A.; Lin, C. -C.; Naylor, Carl H.; Arefin, N.; Metz, M.; Bristol, Robert; Clendenning, Scott B.; Avci, Uygar E.

doi:10.1109/iedm45625.2022.10019524

Cited by 26 publications

(12 citation statements)

References 6 publications

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Section: Process Integration Of 2dms In Device Levelmentioning

confidence: 99%

“…[103] On one hand, the contact resistance shoule be smaller than 40 Ω μm in 2DM devices with a contact length of 10 nm to be competitive withSi-based technology. [104] On the other hand, reducing contact length while ensuring carrier injection efficiency [107] Copyright 2022, IEEE Publishing. e) Benchmark of monolayer MoS 2 FETs I ON at V ds = 1 V with transistors reported in other literature transistors.…”

Section: Contactsmentioning

confidence: 99%

mentioning

confidence: 99%

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Two‐Dimensional Semiconductors: From Device Processing to Circuit Integration

Sheng,

Dong,

Zhu

et al. 2023

Adv Funct Materials

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The atomically thin nature and exceptional electrical properties of 2D materials (2DMs) have garnered significant interest in circuit applications. Researchers have developed circuits based on wafer‐level 2DM fabrication and monolithic integration in the laboratory. Numerous studies have been conducted on discrete device processes; however, circuit manufacturing is a multifaceted and methodical engineering process that demands seamless integration of multiple procedures. Notably, the optimization of crucial processes holds paramount significance in achieving expected results. This review presents the existing research on process integration of 2DM devices and circuit applications. The selection of suitable 2DMs for circuit applications is outlined, considering their excellent theoretical properties and feasible high‐quality growth processes. Drawing on highly mature semiconductor manufacturing process, while incorporating customized key processes, 2DM devices have the potential to strongly compete with, and even outperform, the conventional devices. Finally, the recent circuit applications of 2DMs are also discussed in detail. 2DM integrated circuits (2DM ICs) are now being practically applied in advanced manufacturing, transitioning from laboratory development to fabrication plant deployment. The implementation of underlying 2DM IC fabrication provides effective and unique solutions for More Moore, More than Moore, and Beyond CMOS technology routes.

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Section: Process Integration Of 2dms In Device Levelmentioning

confidence: 99%

Section: Contactsmentioning

confidence: 99%

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Two‐Dimensional Semiconductors: From Device Processing to Circuit Integration

Sheng,

Dong,

Zhu

et al. 2023

Adv Funct Materials

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“…[21][22][23][24] Moreover, a research group has recently explored DG MoS 2 FETs with a channel length of 25 nm, which show a comparable performance to state-ofthe-art Si technology. [25] Thus, the DG architectures of highperformance 2D FETs need to be developed to ensure a long-term continuity of Moore's Law scaling.…”

Section: Introductionmentioning

confidence: 99%

Modulation of Contact Resistance of Dual‐Gated MoS₂ FETs Using Fermi‐Level Pinning‐Free Antimony Semi‐Metal Contacts

et al. 2023

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Achieving low contact resistance (RC) is one of the major challenges in producing 2D FETs for future CMOS technology applications. In this work, the electrical characteristics for semimetal (Sb) and normal metal (Ti) contacted MoS2 devices are systematically analyzed as a function of top and bottom gate‐voltages (VTG and VBG). The semimetal contacts not only significantly reduce RC but also induce a strong dependence of RC on VTG, in sharp contrast to Ti contacts that only modulate RC by varying VBG. The anomalous behavior is attributed to the strongly modulated pseudo‐junction resistance (Rjun) by VTG, resulting from weak Fermi level pinning (FLP) of Sb contacts. In contrast, the resistances under both metallic contacts remain unchanged by VTG as metal screens the electric field from the applied VTG. Technology computer aided design simulations further confirm the contribution of VTG to Rjun, which improves overall RC of Sb‐contacted MoS2 devices. Consequently, the Sb contact has a distinctive merit in dual‐gated (DG) device structure, as it greatly reduces RC and enables effective gate control by both VBG and VTG. The results offer new insight into the development of DG 2D FETs with enhanced contact properties realized by using semimetals.

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“…[5][6][7] Major manufacturers of semiconductor chips have recently reported on the implementation of TMDCs as future channel materials in nextgeneration transistor architectures, such as the gate-all-around (GAA) configuration. [8][9][10] Among TMDCs, ambipolar semiconductors such as WS 2 and WSe 2 have attracted attention owing to their ambipolar transport properties. 11 Ambipolar semiconductors can use both electrons and holes as carriers in a single channel, and they can be either n-or pdoped.…”

mentioning

confidence: 99%

Editors’ Choice—Atomic Layer Etching of Tungsten Disulfide Using Remote Plasma-Induced Oxidation and Wet Etching

You,

Park,

Kim

2023

ECS J. Solid State Sci. Technol.

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WS2 is an emerging semiconductor with potential applications in next-generation device architecture owing to its excellent electrical and physical properties. However, the presence of inevitable surface contaminants and oxide layers limits the performance of WS2-based field-effect transistors (FETs). In this study, the thickness of a WS2 layer was adjusted and its surface was restored to a pristine state by fabricating a recessed-channel structure through a combination of self-limiting remote plasma oxidation and KOH solution etching processes. The reaction between the KOH solution and WOX enabled layer-by-layer thickness control as the topmost oxide layer was selectively removed during the wet-etching process. The thickness of the WS2 layer decreased linearly with the number of recess cycles, and the vertical etch rate was estimated to be approximately 0.65 nm/cycle. Finally, the pristine state was recovered by removing ambient molecules and oxide layers from the surface of the WS2 channel, which resulted in a high-performance FET with a current on/off ratio greater than 106. This method, which provides a facile approach to restoring the pristine surfaces of transition-metal dichalcogenide (TMDC) semiconductors with precise thickness control, has potential applications in various fields such as TMDC-based (opto)electronic and sensor devices.

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Gate length scaling beyond Si: Mono-layer 2D Channel FETs Robust to Short Channel Effects

Cited by 26 publications

References 6 publications

Two‐Dimensional Semiconductors: From Device Processing to Circuit Integration

Two‐Dimensional Semiconductors: From Device Processing to Circuit Integration

Modulation of Contact Resistance of Dual‐Gated MoS₂ FETs Using Fermi‐Level Pinning‐Free Antimony Semi‐Metal Contacts

Editors’ Choice—Atomic Layer Etching of Tungsten Disulfide Using Remote Plasma-Induced Oxidation and Wet Etching

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Gate length scaling beyond Si: Mono-layer 2D Channel FETs Robust to Short Channel Effects

Cited by 26 publications

References 6 publications

Two‐Dimensional Semiconductors: From Device Processing to Circuit Integration

Two‐Dimensional Semiconductors: From Device Processing to Circuit Integration

Modulation of Contact Resistance of Dual‐Gated MoS2 FETs Using Fermi‐Level Pinning‐Free Antimony Semi‐Metal Contacts

Editors’ Choice—Atomic Layer Etching of Tungsten Disulfide Using Remote Plasma-Induced Oxidation and Wet Etching

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Product

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Modulation of Contact Resistance of Dual‐Gated MoS₂ FETs Using Fermi‐Level Pinning‐Free Antimony Semi‐Metal Contacts