Gate oxide damage from polysilicon etching

Gabriel, Calvin T.

doi:10.1116/1.585578

Cited by 69 publications

(16 citation statements)

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“…By comparison, the number of test structures on a wafer ( ) is on the order of 20 000. Consequently, we can neglect the capacitance ratio compared to in the denominator of (8), so it becomes (9) The potential of the silicon substrate is thus the average potential on the gates of the test structures. Since the test structures are located uniformly across the surface of the wafer, we can approximate the potential of the silicon substrate as the average potential across the surface of the wafer.…”

Section: Pre-breakdown Equivalent-circuit Modelmentioning

confidence: 99%

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Plasma-parameter dependence of thin-oxide damage from wafer charging during electron-cyclotron-resonance plasma processing

Friedmann

Shohet

Mau

et al. 1997

IEEE Trans. Semicond. Manufact.

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Abstract-In this work, the effects of plasma-parameter variations on charging damage to polysilicon-gate MOS capacitor test structures exposed to O 2 electron-cyclotron-resonance (ECR) plasmas are investigated. Results will show that charging damage is generated when large potential differences exist across the gate-oxide layers of the MOS capacitor test structures and that these potential differences can only occur in the presence of plasma nonuniformities. These results demonstrate the critical need for plasma uniformity during processing, in particular as device dimensions shrink and gate-oxide thicknesses decrease. The plasma parameters were varied by adjusting the neutral gas pressure and by independently biasing a circular grid and a ring electrode located above the wafer. The damage induced in the test wafers during the plasma exposure was characterized with ramp-voltage breakdown measurements. Radial profiles of the floating potential measured with a Langmuir probe were found to vary nonuniformly when the grid electrode was positively biased due to preferential depletion of electrons relative to ions beneath the grid electrode. An equivalent-circuit model of the test wafer and the wafer-stage electrode predicts that the silicon substrate acquires a potential equal to the average of the wafer surface potential. Comparisons of the calculated profiles of the potential difference across the gate-oxide layers of the test structures and whole-wafer maps of the breakdown-voltage measurements show that the majority of the damage occurs where the oxide potential difference is largest and that the damage only occurs in the presence of plasma nonuniformities.

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Section: Pre-breakdown Equivalent-circuit Modelmentioning

confidence: 99%

“…This damage is the result of exposure to the various particle and energy fluxes present in the plasma environment and for gate oxides can be caused by wafer surface charging, [7]- [9]. The damage generated by this charging is the result of Fowler-Nordheim (F-N) current stressing of thin oxides under floating gates, [10], [11].…”

Section: Introductionmentioning

confidence: 99%

Plasma-parameter dependence of thin-oxide damage from wafer charging during electron-cyclotron-resonance plasma processing

Friedmann

Shohet

Mau

et al. 1997

IEEE Trans. Semicond. Manufact.

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“…However, many studies have shown that the thin oxide under the gate electrode can be damaged during gate etching. [1][2][3][4] This damage probably occurs as a result of charge from the plasma entering the exposed edges of the resist-masked gate electrode. 5,6 Earlier work found that damage occurs primarily at or near the polysilicon endpoint, with subsequent overetching having little effect on it.…”

Section: Introductionmentioning

confidence: 99%

Effect of plasma overetch of polysilicon on gate oxide damage

Gabriel¹,

McVittie

1995

Journal of Vacuum Science &Amp; Technology A: Vacuum, Surfaces, and Films

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Modeling and previous experiments have indicated that charging damage during metal–oxide semiconductor (MOS) polysilicon gate etching occurs just before endpoint when the last of the exposed polysilicon can collect excess plasma currents that cause damage by flowing through the gate oxide. During overetch, this damage mechanism is suppressed by the poor collection efficiency of the exposed polysilicon edges, so damage from this mechanism is expected to remain constant during this period. Although there is an additional edge damage mode where damage can increase during overetch, we here report results showing a decrease in damage with overetch time. The experiment consisted of two lots of fully processed complementary MOS wafers where the polysilicon overetch percentage was varied from 0% to 110%. The etch tool was a triode system that showed antenna dependent charging damage. The test structures were large area capacitors with a 10.5 nm thin oxide whose breakdown statistics were measured after the full process, including anneals. Both the n-channel and p-channel devices showed damage which decreased with overetch time. The damage was significantly worse for the n-channel devices—the mean n-channel gate oxide breakdown voltage was 3 V at endpoint compared to 11.5 V after 110% overetch. The effect was repeated in that both lots showed the same results. The results indicate an apparent annealing during overetch. In the past, radio frequency (rf) annealing has been reported for e-beam damage with a proposed mechanism involving rf heating and carrier motion. We consider this unlikely and suspect that low plasma currents collected by the gate edge could be playing a role in the annealing; however, etching of the exposed gate oxide during overetch may also be important. The n- and p-channel differences can be explained by a voltage drop across the n well which reduces the tunnel current through the p-channel gate oxides.

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“…As feature sizes drop below 100 nm, UV radiation and feature charging are predicted to be the primary cause of device damage. 98 In addition, particle generation, which is extensive in reactive plasma atmospheres, is a concern, and methods to both minimize particle generation and remove particles after etch and deposition are needed. [99][100][101][102] Small feature sizes (Ͻ500 nm) and low pressure (Ͻ5 mTorr) reactors have generated their own set of pattern distortions and uniformity problems including aspect ratio dependent etching and microloading.…”

Section: Plasma Processingmentioning

confidence: 99%