Gate oxide damage in a high density inductively coupled plasma

Gabriel, Calvin T.

doi:10.1116/1.587100

Cited by 20 publications

(8 citation statements)

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“…-There has been a tremendous growth in knowledge in low temperature plasma materials processing/plasma etch science and technology since the first ALE studies. Examples are a) control of ionization, dissociation and uniformity across wafer, 1,3,107,108 b) ion energy control, 109 including using shaped waveforms, 96 c) pulsed plasma science and technology, 5 d) control of wafer charging and damage effects, [110][111][112] e) plasma characterization and metrology, 113,114 f) understanding of the control of plasma-polymer interactions, Line Edge Roughness, Line Width Roughness, CD and CD variation, 115 advanced modeling and simulations of all of the above, 116 and tremendous growth in advanced hardware engineering and capabilities.…”

Section: Scientific and Technological Basis Of Alementioning

confidence: 99%

Atomic Layer Etching at the Tipping Point: An Overview

Oehrlein

Metzler

2015

ECS J. Solid State Sci. Technol.

232

162

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The ability to achieve near-atomic precision in etching different materials when transferring lithographically defined templates is a requirement of increasing importance for nanoscale structure fabrication in the semiconductor and related industries. The use of ultra-thin gate dielectrics, ultra thin channels, and sub-20 nm film thicknesses in field effect transistors and other devices requires near-atomic scale etching control and selectivity. There is an emerging consensus that as critical dimensions approach the sub-10 nm scale, the need for an etching method corresponding to Atomic Layer Deposition (ALD), i.e. Atomic Layer Etching (ALE), has become essential, and that the more than 30-year quest to complement/replace continuous directional plasma etching (PE) methods for critical applications by a sequence of individual, self-limited surface reaction steps has reached a crucial stage. A key advantage of this approach relative to continuous PE is that it enables optimization of the individual steps with regard to reactant adsorption, self-limited etching, selectivity relative to other materials, and damage of critical surface layers. In this overview we present basic approaches to ALE of materials, discuss similarities/crucial differences relative to thermal and plasma-enhanced ALD, and then review selected results on ALE of materials aimed at pattern transfer. The overview concludes with a discussion of opportunities and challenges ahead. A requirement of increasing importance for nanoscale device fabrication is the ability to achieve atomic scale etching control and materials selectivity during pattern transfer.1-8 An etching method corresponding to Atomic Layer Deposition (ALD), i.e. Atomic Layer Etching (ALE), is expected to satisfy these needs as critical dimensions continue to shrink below the 10 nm scale.Demonstrations of self-limited dry etching methods capable of near-atomic resolution have a long history in the dry etching community and a brief review will be presented below. Key challenges for these approaches have been specialized equipment, long process times and low throughput.9,10 However, a recent demonstration using a commercial plasma etch tool 10 and activities within the dry etching community 11 provide indications that the situation has changed, and that we may have reached for ALE the Tipping Point which Gladwell defined as the "the moment of critical mass, the threshold, the boiling point" when "ideas and products and messages and behaviors spread like viruses do".12 This is due to several factors, including unprecedented demands on dry etching technology introduced by the semiconductor device evolution according to Moore's law that can be satisfied by atomic layer etching, advanced capabilities in plasma etch, and the existence of a critical level of information on plasma etch and ALD methods as applied in the semiconductor fabrication space.In this article we will provide a review of background of these approaches, and focus on issues that have to be overcome for widespread implement...

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Section: Scientific and Technological Basis Of Alementioning

confidence: 99%

Atomic Layer Etching at the Tipping Point: An Overview

Oehrlein

Metzler

2015

ECS J. Solid State Sci. Technol.

232

162

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“…[1][2][3][4] ''Ion and electron currents do not have to balance locally through the rf cycle, although there must be a net balance over the electrode as a whole.'' [1][2][3][4] ''Ion and electron currents do not have to balance locally through the rf cycle, although there must be a net balance over the electrode as a whole.''…”

Section: Understanding the Problemmentioning

confidence: 99%

Degradation measurements using fully processed test transistors in high density plasma reactors for failure analysis

Muniandy¹

1997

Journal of Vacuum Science &Amp; Technology B: Microelectronics and Nanometer Structures Processing, Measurement, and Phenomena

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Articles you may be interested inMechanism and lifetime prediction method for hot-carrier-induced degradation in lateral diffused metal-oxidesemiconductor transistors Appl. Phys. Lett. 92, 243501 (2008); 10.1063/1.2947588Dependence of the performance and reliability of n-metal-oxide-silicon field effect transistors on interlayer dielectric processing Nanopotentiometry: Local potential measurements in complementary metal-oxide-semiconductor transistors using atomic force microscopy High temperature performance mapping and failure analysis of 4H-silicon carbide mosfets AIP Conf.The objective of this study was for it to serve as a guide for understanding high density plasma induced damage during wafer fabrication and etchback for device debug, electron-beam, and failure analysis. A study of electrical degradation of packaged and fully processed transistors that were functionally etched back was carried out. Two high density plasma technologies, electron cyclotron resonance ͑ECR͒ and inductively coupled plasma ͑ICP͒, from various vendors, were evaluated. Transconductance (gm), threshold voltage (Vt), subthreshold slope, and gate leakage (Ig) were measured before and after the functional etch. Degradation took place even without polysilicon being directly exposed to the plasma. It was found that there is a strong correlation between the threshold voltage shift, and gate current shift, and they exhibit a bimodal relationship. The gate edge intensive transistor was most susceptible to degradation. The design of the etchers seemed to be the key factor rather than the choice of technology ͑ECR or ICP͒ with regard to transistor degradation. Gate oxide breakdown due to the charging of metal lines, caused by nonuniform electrical charging of the surface, adequately explains the observed transistor parameter shifts.

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“…It is well known that the accumulation of electrons on the SiO 2 layer causes charging damage to the gate SiO 2 layer. [17][18][19][20][21][22] It has been reported that SiO 2 damage during SiO 2 deposition and etching with a plasma process is caused by the accumulated electrical charges passing through the SiO 2 layer, where the charges are supplied to the gate electrodes of the antenna metal oxide semiconductor (MOS) capacitor from the plasma during the plasma process. [23][24][25] When the metal layer is deposited, it forms islands on the SiO 2 layer upon magnetron sputtering, and electrical charges accumulate on the SiO 2 layer.…”

Section: Introductionmentioning

confidence: 99%