Gate-oxide thickness effects on hot-carrier-induced degradation in n-MOSFETs

Gu, Y.; Yuan, J.S.

doi:10.1109/southc.1996.535099

Cited by 2 publications

(2 citation statements)

References 11 publications

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“…In addition, 180 nm Si of Figure 6 b shows 2.85% and 2.32% for the basic size and the double channel widths, respectively. The maximum amplitude variations could be generated by induced γ-ray radiation, as considered with previous results [ 7 ] and Equations (8) and (9), thus this phenomenon is related to the steady decline of trans-conductance, including a threshold voltage term, and the steady increase of the output resistance [ 28 , 29 ]. Moreover, Figure 6 a,b shows that increasing the channel width without modifying fabrication processes could deliver more radiation tolerance against amplitude variations.…”

Section: Resultssupporting

confidence: 55%

Integrated Circuit Design for Radiation-Hardened Charge-Sensitive Amplifier Survived up to 2 Mrad

Lee

Cho

Unruh

et al. 2020

Sensors

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According to the continuous development of metal-oxide semiconductor (MOS) fabrication technology, transistors have naturally become more radiation-tolerant through steadily decreasing gate-oxide thickness, increasing the tunneling probability between gate-oxide and channel. Unfortunately, despite this radiation-hardened property of developed transistors, the field of nuclear power plants (NPPs) requires even higher radiation hardness levels. Particularly, total ionizing dose (TID) of approximately 1 Mrad could be required for readout circuitry under severe accident conditions with 100 Mrad around a reactor in-core required. In harsh radiating environments such as NPPs, sensors such as micro-pocket-fission detectors (MPFD) would be a promising technology to be operated for detecting neutrons in reactor cores. For those sensors, readout circuits should be fundamentally placed close to sensing devices for minimizing signal interferences and white noise. Therefore, radiation hardening ability is necessary for the circuits under high radiation environments. This paper presents various integrated circuit designs for a radiation hardened charge-sensitive amplifier (CSA) by using SiGe 130 nm and Si 180 nm fabrication processes with different channel widths and transistor types of complementary metal-oxide-semiconductor (CMOS) and bipolar CMOS (BiCMOS). These circuits were tested under γ–ray environment with Cobalt-60 of high level activity: 490 kCi. The experiment results indicate amplitude degradation of 2.85%–34.3%, fall time increase of 201–1730 ns, as well as a signal-to-noise ratio (SNR) of 0.07–11.6 dB decrease with irradiation dose increase. These results can provide design guidelines for radiation hardening operational amplifiers in terms of transistor sizes and structures.

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Section: Resultssupporting

confidence: 55%

Integrated Circuit Design for Radiation-Hardened Charge-Sensitive Amplifier Survived up to 2 Mrad

Lee

Cho

Unruh

et al. 2020

Sensors

View full text Add to dashboard Cite

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“…When the gate oxide is thinner, the gate will be able to control the channel more efficiently. Also, as the gate oxide becomes thinner, the damaged interface region from hot carrier effects is moved into the drain region [33]. This reduces the hot electron effect on the device as the effective damage length in the active channel will be reduced [33].…”

Section: Equation 3-1 = • ≡ •mentioning

confidence: 99%

Minimizing nMOS Edge Leakage in Fully Depleted Silicon-on-Insulator CMOS Using Poly-Buffered LOCOS Isolation

Trifoli¹

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A process has been designed, implemented and tested to minimize edge-leakage effects in fully depleted silicon-on-insulator (FD SOI) nMOSFET (nMOS) devices encountered in previous student project SOI CMOS fabrication runs in the Carleton University Microfabrication Laboratory. A layout with test arrays, including enclosed geometry transistors, was designed to perform a test fabrication run. The process uses optimized oxidation steps and Poly-Buffered LOCal Oxidation of Silicon (PBL) isolation with minimal mask steps and fabrication time. The fabricated test transistors revealed that some subthreshold edge leakage was still present in the nMOS devices. SEM imaging showed that the field oxide had been almost entirely unintentionally etched away during processing. This reduction in the field oxide thickness creates parasitic edge transistors. Sentaurus simulations imply that if not for this field oxide loss, the fabricated nMOS devices would have had minimal leakage with no kink in the subthreshold curve.

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Gate-oxide thickness effects on hot-carrier-induced degradation in n-MOSFETs

Cited by 2 publications

References 11 publications

Integrated Circuit Design for Radiation-Hardened Charge-Sensitive Amplifier Survived up to 2 Mrad

Integrated Circuit Design for Radiation-Hardened Charge-Sensitive Amplifier Survived up to 2 Mrad

Minimizing nMOS Edge Leakage in Fully Depleted Silicon-on-Insulator CMOS Using Poly-Buffered LOCOS Isolation

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