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The Gate-oxide thickness effects on hot-carrier-induced degradation have been investigated for submicron MOSFETs. A thinner gate oxide gives a higher substrate current, but reduced hot electron effects. This is because the thin-gate-oxide device has smaller mobility and threshold voltage degradation due to a shift of damaged interface region towards the drain contact. In this work, the analytical substrate and drain current model has been derived. The model predictions have good agreement with the experimental data for submicron MOSFETs with different oxide thicknesses.

Wafer thinning is a crucial technique for high‐efficiency solar cells. Herein, an inverted pyramid (IP) texture is prepared on a 35 μm‐thick flexible silicon (Si) wafer with a standard area of 156 × 156 mm2. Based on the experimental results, an ultrathin bifacial passivated emitter and rear cell (PERC) with IP textures using PC1D simulation is designed. The influence of wafer thickness, IP texture, bifacial structure, thickness of the antireflection coating, and doping concentration on device performance is investigated. The results show that the ultrathin IP‐based bifacial PERC possesses better output performance than the traditional cell. Finally, a simulated maximum efficiency of 23.44% is obtained using PC1D software, with an open‐circuit voltage of 0.7127 V and a short‐circuit current of 9.272 A. This ultrathin PERC with IP textures provides an effective way to improve the efficiency of ultrathin silicon solar cells.

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The analytical equations of collector and base currents and emitter—base and collector—base diffusion capacitances of the bipolar junction transistor in saturation have been reviewed and updated. Comparisons of three base profiles (uniform, exponential, and Gaussian) in terms of electron current density, transconductance, diffusion capacitance, and base transit time are presented.