2021
DOI: 10.1116/6.0000871
|View full text |Cite
|
Sign up to set email alerts
|

Gate spacers etching of Si3N4 using cyclic approach for 3D CMOS devices

Abstract: In this work, we optimize a CH 3 F/O 2 /He/SiCl 4 chemistry to etch silicon nitride gate spacers for 3D CMOS devices in a 300 mm inductively coupled plasma reactor. The chemistry has high directivity and high selectivity to Si and SiO 2 . A cyclic approach, which alternates this chemistry with a CH 2 F 2 /O 2 /CH 4 /He plasma, is investigated. Using quasi in situ x-ray photoelectron spectroscopy and ellipsometry measurements, etching mechanisms are proposed to explain the results obtained. As a result of proce… Show more

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...
2
1
1

Citation Types

0
4
0

Year Published

2023
2023
2024
2024

Publication Types

Select...
4

Relationship

1
3

Authors

Journals

citations
Cited by 4 publications
(4 citation statements)
references
References 39 publications
0
4
0
Order By: Relevance
“…What is specific to Si3N4 in comparison of Si, SiO2 or SiCO to explain that etching is favored over silicon oxifluoride deposition? The larger Si-O (800 kJ.mol -1 ) than Si-N (437 kJ.mol -1 ) bond energy 27 is sometimes assumed as the cause of etch selectivity 15,21,28 .…”
Section: Discussionmentioning
confidence: 99%
See 1 more Smart Citation
“…What is specific to Si3N4 in comparison of Si, SiO2 or SiCO to explain that etching is favored over silicon oxifluoride deposition? The larger Si-O (800 kJ.mol -1 ) than Si-N (437 kJ.mol -1 ) bond energy 27 is sometimes assumed as the cause of etch selectivity 15,21,28 .…”
Section: Discussionmentioning
confidence: 99%
“…As there is a significant SiOxFy deposition when landing on c-Si of the active, some oxide accumulation might occur around the active corner and prevent parasitic spacer etch removal on 3D architectures. Thus, the necessity to cycle the SiCl4-based etch process with a carefully designed oxide etch step in order to overcome this issue has been demonstrated recently 7 , followed by process development and optimization of this etching sequence 15 . However, mechanisms of SiOxFy selective deposition on c-Si and SiO2 while Si3N4 is etched remain unclear.…”
Section: Introductionmentioning
confidence: 99%
“…At the same time, it provides excellent coverage in field-effect transistors while maintaining its good carrier mobility [10,11]. With the development of technology, researches on Si 3 N 4 have became more mature, the current technology can make good use of it chemistry has high directivity and high selectivity to Si and SiO2 [12], it might be a good substitute of SiO2 for gate dielectric.…”
Section: Relevant Theoriesmentioning
confidence: 99%
“…The Si 3 N 4 spacer around the fin made of Si is required to be etched without loss of the fin. [9][10][11] Here, it is necessary to preserve the Si 3 N 4 around the dummy gate without etching it. Isotropic Si 3 N 4 etching causes loss of Si 3 N 4 spacer around the dummy gate; therefore, anisotropic etching using ion energy must be applied for the Si 3 N 4 spacer etching.…”
Section: Introductionmentioning
confidence: 99%