2015
DOI: 10.1088/0268-1242/31/2/024001
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Gate stack engineering for GaN lateral power transistors

Abstract: Developing optimal gate-stack technology is a key to enhancing the reliability and performance of GaN insulated-gate devices for high-voltage power switching applications. In this paper, we discuss current challenges and review our recent progresses in gate-stack technology development toward high-performance and high-reliability GaN power devices, including (1) interface engineering that creates a high-quality dielectric/III-nitride interface with low trap density; (2) barrier-layer engineering that enables o… Show more

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Cited by 10 publications
(8 citation statements)
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“…[ 158,159 ] Hence, interface engineering has been aimed to passivate Ga dangling bonds and compensate N vacancies, which was implemented by applying in situ NH 3 /Ar/N 2 remote plasma pretreatment (RPP) in a plasma‐enhanced atomic layer deposition (PEALD) system. [ 148,159,160 ] A crystalline AlN was observed when the NH 3 /Ar/N 2 RPP was implemented before Al 2 O 3 deposition. The AlN interlayer not only provides superior passivation quality but also prevent the GaN oxidation during Al 2 O 3 deposition.…”
Section: Mis Structurementioning
confidence: 99%
“…[ 158,159 ] Hence, interface engineering has been aimed to passivate Ga dangling bonds and compensate N vacancies, which was implemented by applying in situ NH 3 /Ar/N 2 remote plasma pretreatment (RPP) in a plasma‐enhanced atomic layer deposition (PEALD) system. [ 148,159,160 ] A crystalline AlN was observed when the NH 3 /Ar/N 2 RPP was implemented before Al 2 O 3 deposition. The AlN interlayer not only provides superior passivation quality but also prevent the GaN oxidation during Al 2 O 3 deposition.…”
Section: Mis Structurementioning
confidence: 99%
“…Nevertheless, the use of SiO 2 as gate dielectric has been reported to yield a more stable V T under PBTI stress than Al 2 O 3 [63]. N incorporation into the bulk of Al 2 O 3 or at the interface with the semiconductor has been shown to improve V T stability [70], [71]. Severe V T shifts have been observed in devices that use SiN x as gate dielectric [59], [68], [72], However, there are also reports that indicate that different deposition techniques yield widely different stability characteristics [59].…”
Section: B Bias-temperature Instability Associated With the Gate Dielectric Of Gan Mis-hemtsmentioning
confidence: 99%
“…2). Other approaches for normally off GaN HFETs use recessing of the AlGaN barrier with an insulating gate, enhancement‐mode metal–insulator–semiconductor FET (MISFETs) are realised [9]. However, no intrinsic gate insulator exists for GaN and extrinsic insulator materials suffer from charging with associated hysteresis effects and threshold voltage instabilities [10].…”
Section: Lateral Gan Transistorsmentioning
confidence: 99%