Ge nFET with high electron mobility and superior PBTI reliability enabled by monolayer-Si surface passivation and La-induced interface dipole formation

Arimura, Hiroaki; Sioncke, Sonja; Cott, Daire; Mitard, J.; Conard, Thierry; Vanherle, W.; Loo, Roger; Favia, P.; Bender, Hugo; Meersschaut, Johan; Witters, L.; Mertens, Hans; Franco, J.; Ragnarsson, Lars‐Åke; Pourtois, Geoffrey; Heyns, Marc; Mocuta, A.; Collaert, N.; Thean, Aaron

doi:10.1109/iedm.2015.7409752

Cited by 29 publications

(33 citation statements)

References 9 publications

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“…For the samples shown in Figure 9, the oxide was removed by a wet-chemical treatment without in-situ bake. For SiH 4 , enhanced Ge segregation into the Si layer was indeed confirmed on samples that did receive a pre-epi bake at 600…”

Section: In Ref 2)mentioning

confidence: 80%

“…1,2,4,6,15,19,20 The benefit of the Si passivation layer above GeO x -based gate stacks is its potential to improve Bias Temperature Instability (BTI) reliability. 4,36 It is important to avoid surface segregation of Ge through the Si layer during the epitaxial growth as this leads to an increase of the interfacial trap density and distribution in the finalized gate stack. 20 On the other hand, the Si passivation layer has to be sufficiently thin to approach an Equivalent Oxide Thickness (EOT) close to 1 nm as implemented in the current 14 nm-node Fin-FET.…”

Section: In Ref 2)mentioning

confidence: 99%

“…Si GAA FETs can be fabricated from Si/SiGe with 25-30% Ge. The layers with the required steep compositional gradients (from SIMS we extracted ∼1.5 nm wide interface between Si and SiGe) can be easily grown using standard process conditions and conventional Si and Ge precursors such as SiH 4 42 Recently, we demonstrated Si GAA FETs made of vertically stacked horizontal nanowires with excellent short-channel characteristics. 27 An ultimate scaling of this technology assumes the use of either Si or Ge and SiGe with high Ge contents close to 50%.…”

Section: In Ref 2)mentioning

confidence: 99%

“…The second epi step is the deposition of a Si-passivation layer on top of the different fin surfaces, which is one possible way to improve the high-k/channel interface. 1,2,4,6,15,19,20 The process flow also contains the epitaxial growth of the Source/Drain contacts to increase the uni-axial strain in the channel, although this strain engineering technique becomes less efficient with reducing device dimensions. 12,13 Reduced device dimensions set also a clear need to reduce the S/D contact resistivity as this might limit device performance.…”

mentioning

confidence: 99%

“…[1][2][3][4][5][6][7] These so-called high mobility materials are implemented in new device concepts and novel architectures, for example tunnel FETs and gate-all-around devices, in order to meet the power and performance requirements. Reference 7 gives an overview of the innovations in materials and new device concepts that will be needed to continue Moore's law to sub-7nm technology nodes.…”

mentioning

confidence: 99%

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Processing Technologies for Advanced Ge Devices

Loo

Hikavyy

Witters

et al. 2016

ECS J. Solid State Sci. Technol.

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With the continued scaling of CMOS devices below the 10 nm node, process technologies become more and more challenging as the allowable thermal budget for device processing continuously reduces. This is especially the case during epitaxial growth, where a reduction of the thermal budget is required for a number of potential reasons for example to avoid uncontrolled layer relaxation of strained layers, surface reflow of narrow fin structures, as well as doping diffusion and material intermixing. Further aspects become even more challenging when Ge is used as a high-mobility channel material and when the device concept moves from a FinFET design to a nanowire FET design (also called Gate-All-Around FET). In this contribution we address some of the challenges involved with the integration of high mobility Group IV materials in these advanced device structures.

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Section: In Ref 2)mentioning

confidence: 80%

Section: In Ref 2)mentioning

confidence: 99%

Section: In Ref 2)mentioning

confidence: 99%

mentioning

confidence: 99%

mentioning

confidence: 99%

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Processing Technologies for Advanced Ge Devices

Loo

Hikavyy

Witters

et al. 2016

ECS J. Solid State Sci. Technol.

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III-V Devices and Technology for CMOS

Waldron

2018

High Mobility Materials for CMOS Applications

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Scavenging Segregated Ge on Thin Single-Crystal Si Epitaxially Grown on Ge

Cheng

Wan

Chu

et al. 2021

ACS Appl. Electron. Mater.

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Single-crystal Si with six monolayers in thickness was epitaxially grown on epi-Ge(001). The Si surface is characterized with the Ge atoms segregated from the underlying epi-Ge. Some of the Ge atoms bond with the Si inside the film. Upon O2 exposure at room temperature, both the Si and Ge surface atoms are simultaneously oxidized to give rise to four Si charge states and Ge suboxides, respectively. The subsequent in situ annealing at 500 °C under ultra-high vacuum moved the oxygen atom in the Ge suboxides to bond with the nearby Si atom. The annealing also caused the diffused Ge inside the epi-Si to segregate to the surface. The processes of O2 exposure followed by annealing were repeated three times resulting in an oxidized Si/Ge surface having only the four Si oxidized states without GeO x , but with a very small amount of segregated Ge. Using the scavenging process in reducing the segregated Ge prior to the high-κ deposition, the C–V hysteresis of the high-κ/epi-Si/n-Ge(001) metal-oxide-semiconductor (MOS) capacitors decreased more than two times, meaning that the electron traps contributed from the GeO x in the high-κ/epi-Si/Ge(001) are reduced.

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Ge nFET with high electron mobility and superior PBTI reliability enabled by monolayer-Si surface passivation and La-induced interface dipole formation

Cited by 29 publications

References 9 publications

Processing Technologies for Advanced Ge Devices

Processing Technologies for Advanced Ge Devices

III-V Devices and Technology for CMOS

Scavenging Segregated Ge on Thin Single-Crystal Si Epitaxially Grown on Ge

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