Generating Efficient Custom FPGA Soft-Cores for Control-Dominated Applications

L'Hours, Ludovic

doi:10.1109/asap.2005.37

Cited by 10 publications

(7 citation statements)

References 13 publications

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“…The front-end of our proposed design-flow leverages from GeCoS [17], an open source retargetable compiler framework for ASIPs (Application Specific Instruction Set Processors). To be precise, we used GeCoS compilation front-end to generate intermediate representations (IRs) that are in the form of CDFGs (Control and Data Flow Graphs).…”

Section: A Front-end: C To Vhdl Descriptionsmentioning

confidence: 99%

A design-flow for high-level synthesis and resource estimation of reconfigurable architectures

Pasha

Siddiqui

Farooq

2015

2015 10th International Conference on Design &Amp; Technology of Integrated Systems in Nanoscale Era (DTIS)

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Field Programmable Gate Arrays (FP-GAs), due to their programmability, have become a popular design choice for control and processing blocks of an embedded system. However, this flexibility makes them larger, slower and less power-efficient than Application Specific Integrated Circuits (ASICs) and hinders their use in low-area and low-power applications. On the other hand, ASICs have their inherent drawbacks like lack of programmability and inflexibility. The solution is reconfigurable architectures that have improved flexibility over ASICs and better resource utilization than FPGAs. However, designing a reconfigurable architecture is a daunting task in itself due to lack of high-level design-flow support. This paper proposes an automated design-flow for system-level synthesis and resource estimation for generic as well as custom reconfigurable architectures. The experimental results show that the generated reconfigurable architectures are 79% more area and 76% more power efficient than generic academic FPGA-based implementations.

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Section: A Front-end: C To Vhdl Descriptionsmentioning

confidence: 99%

A design-flow for high-level synthesis and resource estimation of reconfigurable architectures

Pasha

Siddiqui

Farooq

2015

2015 10th International Conference on Design &Amp; Technology of Integrated Systems in Nanoscale Era (DTIS)

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“…The different blocks of the SoPC are interconnected by means of specific, standarized buses [53] inside the FPGA. This facilitates the reusability of the cores and distributed design.…”

Section: System On Chipmentioning

confidence: 99%

Matrix Converter Protection and Computational Capabilities Based on a System on Chip Design With an FPGA

Ormaetxea

Andreu

Kortabarria

et al. 2011

IEEE Trans. Power Electron.

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The matrix converter (MC) presents a promising topology that needs to overcome certain barriers (complexity of the modulation and control techniques, protection systems, etc.) in order to gain a foothold in the industry. Traditionally, the MC has been controlled by means of a DSP, together with a fieldprogrammable gate array (FPGA). The sole aim of the latter is to perform the safe commutation of the converter. This involves a waste of resources, as the excellent features of the FPGA are infrautilized by the control system. This paper deals with the implementation of the double-sided space vector modulation (DS SVM), commutation, reference-frame changes, and protection of the MC through a series of hardware blocks (cores) integrally implemented in an FPGA. The designed cores are technology-independent descriptions, which means that the developed design can be used in the FPGAs of any manufacturer. Moreover, the proposed design, which has been validated experimentally, has obviated the need to use a DSP. Likewise, given that all the processing capabilities have been integrated in a single chip, it can be said that an FPGA-based system on a programmable chip (SoPC) has been designed. Due to the computational capacity of the developed cores, processing time is reduced to the order of nanoseconds. This allows a response in real time and very high modulation frequencies can be attained. Moreover, these cores operate independently, and simultaneously, therefore obviating the need for sequential control and its resulting latencies and leading to an increase in the safety of the MC.Index Terms-Core, field-programmable gate array (FPGA), matrix converter (MC), modulation, protection, system on chip (SoC).

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“…3) is based on GeCoS compiler infrastructure [21], a retargetable C compiler framework, whose instruction selection phase is retargeted to generate the assembly instructions for our simplified datapath model. This low-level program representation is then used to generate VHDL descriptions of (i) a custom datapath which implements the minimum required set of operations for the task at hand, and (ii) a micro-coded FSM that controls different entities of the datapath (for details of our design-flow, see [22]) .…”

Section: A) Automatic Generation Of Micro-tasksmentioning

confidence: 99%

A novel approach for ultra low-power WSN node generation

Pasha¹,

Derrien²,

Sentieys³

2010

IET Irish Signals and Systems Conference (ISSC 2010)

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Wireless Sensor Network (WSN) technology is now emerging with applications in various domains of human life e.g. medicine, environmental monitoring and military surveillance etc. WSN systems consist of low-cost and low-power sensor nodes that communicate efficiently over short distances. It has been shown that power consumption is the biggest design constraint for such systems. Currently, WSN nodes are being designed using low-power microcontrollers. However, their power dissipation is still orders of magnitude too high and limits the wide-spreading of WSN technology. In this paper, we propose an alternative approach that uses hardware specialization and power-gating to generate distributed hardware micro-tasks. We target control-oriented tasks running on WSN nodes and present, as a case study, a lamp-switching application. Our approach is validated experimentally and shows prominent power gains over software implementation on a low-power microcontroller such as the MSP430.

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Generating Efficient Custom FPGA Soft-Cores for Control-Dominated Applications

Cited by 10 publications

References 13 publications

A design-flow for high-level synthesis and resource estimation of reconfigurable architectures

A design-flow for high-level synthesis and resource estimation of reconfigurable architectures

Matrix Converter Protection and Computational Capabilities Based on a System on Chip Design With an FPGA

A novel approach for ultra low-power WSN node generation

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