Genetic Algorithm Based Approach To Circuit Partitioning

Gill, Sandeep Singh; Chandel, Rajeevan; Chandel, Ashwani Kumar

doi:10.7763/ijcee.2010.v2.136

Cited by 6 publications

(2 citation statements)

References 27 publications

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“…Another essential method developed by Jigang and Srikanthan [4] is efficient for hardware and software partitioning, which is concerned with improving the system's power estimation and overall running time. Gill et al [5] suggested a genetic algorithm-based strategy for circuit partitioning, in which they discovered the average minimum and average net cut of circuits. They do, however, reveal that most previous methodologies are insufficient in terms of intelligent chromosomal selection for enhanced time.…”

Section: Issn: 0067-2904mentioning

confidence: 99%

“…(4) and B avg *(1-α/100)<=B i <=B avg *(1+α/100) (5) where B i represents the area of partition i. Since in the partitioning algorithm, area of each partition should be nearly equal with slight deviation, B i should be between B avg *(1-β/100) and B avg *(1+ β /100), where B avg = (sum of areas of all modules / number of partitions) and β is the imbalance factor.…”

Section: Net Cut Minimizationmentioning

confidence: 99%

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Multi-Objective Genetic Algorithm-Based Technique for Achieving Low-Power VLSI Circuit Partition

Roy,

Banerjee

2023

Iraqi Journal of Science

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Minimizing the power consumption of electronic systems is one of the most critical concerns in the design of integrated circuits for very large-scale integration (VLSI). Despite the reality that VLSI design is known for its compact size, low power, low price, excellent dependability, and high functionality, the design stage remains difficult to improve in terms of time and power. Several optimization algorithms have been designed to tackle the present issues in VLSI design. This study discusses a bi-objective optimization technique for circuit partitioning based on a genetic algorithm. The motivation for the proposed research is derived from the basic concept that, if some portions of a circuit's system are deactivated during the processor's idle time, the circuit's power consumption is automatically reduced. To reduce the overall system's power consumption, maximization of sleep time and minimization of net cuts are required. To achieve these, an effective fitness function has been constructed in such a way that the balance criteria are also maintained. The approach has been tested on a set of net lists from the ISPD'98 benchmark suite, each containing 10 to 30 nodes. The experimental results are compared with two existing methods that clearly indicate the acceptability of the suggested method. The suggested strategy achieves an average reduction of 24.69% and 31.46% for net cut, whereas average extensions of 15.20% and 12.31% are observed in sleep time when compared with two existing methods. The proposed method also achieves an average power efficiency of 14.98% and 12.09% with respect to these two state-of-the-art methods.

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Section: Issn: 0067-2904mentioning

confidence: 99%

Section: Net Cut Minimizationmentioning

confidence: 99%

Multi-Objective Genetic Algorithm-Based Technique for Achieving Low-Power VLSI Circuit Partition

Roy,

Banerjee

2023

Iraqi Journal of Science

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Soft Computing Approach for VLSI Mincut Partitioning: The State of the Arts

Maity

Saha

Maulik

et al. 2014

Advances in Intelligent Systems and Computing

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Hybrid Partitioning Algorithm for Area Minimization in Circuits

Swetha

Devi²,

Yousef

2015

Procedia Computer Science

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Area miniaturization is the essence of compaction of any application circuit in chip designing. The physical design stages involve virtual design realizations iterated for their efficiency. For this purpose, the CAD algorithms offer a variety of solutions depending on the needs and specifications of the designer. The use of EDA tools help in visualization of the effects of design algorithms on the circuit performance and the dimensions of the floor area occupied by the design. This paper demonstrates the effect of the hybrid algorithm on the circuit design. In this paper the effect of applying the move based partitioning algorithms KL,FM to circuitsand optimizing the cells of the circuit using Hybrid Genetic Algorithm (HGA) is discussed. The results suggest that, this approach on circuits provides scope to unify the stages of physical design stages of partitioning and placement and also optimize the area parameter of a physical design process.

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Genetic Algorithm Based Approach To Circuit Partitioning

Cited by 6 publications

References 27 publications

Multi-Objective Genetic Algorithm-Based Technique for Achieving Low-Power VLSI Circuit Partition

Multi-Objective Genetic Algorithm-Based Technique for Achieving Low-Power VLSI Circuit Partition

Soft Computing Approach for VLSI Mincut Partitioning: The State of the Arts

Hybrid Partitioning Algorithm for Area Minimization in Circuits

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