Genetic framework for the high level optimisationof low power VLSI DSP systems

Bright, M. S.; Arslan, Tughrul

doi:10.1049/el:19960795

Cited by 15 publications

(2 citation statements)

References 10 publications

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“…The evolution process generally eliminates the bad genes and maintains the good genes to generate better solutions. This concept has been recently applied to solve a range of complex VLSI combinatorial optimization problems [23,24,27,28]. In this kind of approach, the feasible solution is usually encoded into a binary string called chromosome.…”

Section: Genetic Algorithmsmentioning

confidence: 99%

Total Power Optimization for Combinational Logic Using Genetic Algorithms

Hung

Xie

Narayanan

et al. 2009

J Sign Process Syst Sign Image Video Technol

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Power consumption is a top priority in high performance circuit design today. Many low power techniques have been proposed to tackle the ever serious, highly pressing power consumption problem, which is composed of both dynamic and static power in the nanometer era. The static power consumption nowadays receives even more attention than that of dynamic power consumption when technology scales below 100 nm. In order to mitigate the aggressive power consumption, various existing low power techniques are often used; however, they are often applied independently or combined with two or at most three different techniques together, and that is not sufficient to address the escalating power issue. In this paper, we present a power optimization framework for the minimization of total power consumption in combinational logic through multiple V dd assignment, multiple V th assignment, device sizing, and stack forcing, while maintaining performance requirements. These four power reduction techniques are properly encoded into the genetic algorithm and evaluated simultaneously. The overhead imposed by the insertion of level converters is also taken into account. The effectiveness of each power reduction mechanism is verified, as are the combinations of different approaches. Experimental results are presented for a number of 65 nm benchmark circuits that span typical circuit topologies, including inverter chains, SRAM decoders, multiplier, and a 32 bit carry adder. Our experiments show that the combination of four low power techniques is the effective way to achieve low power budget. The framework is general and can be easily extended to include other design-time low power techniques, such as multiple gate length or multiple gate oxide thickness.

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Section: Genetic Algorithmsmentioning

confidence: 99%

Total Power Optimization for Combinational Logic Using Genetic Algorithms

Hung

Xie

Narayanan

et al. 2009

J Sign Process Syst Sign Image Video Technol

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“…Therefore, one way of reducing the power consumption of digital filters, is to reduce the amount of switched capacitance during its operation. Example approaches in the literature for reducing the switched capacitance of digital filters are coefficient ordering [2], data block processing [3], dynamically minimising filter order [4], choice of appropriate coding techniques [1,5], and the application of high level transformations [6,7]. This paper presents a new multiplication algorithm for low-power implementation of digital filters on CMOS DSPs.…”

Section: Introductionmentioning

confidence: 99%

A coefficient segmentation algorithm for low power implementation of FIR filters

Erdogan¹,

Arslan²

ISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI (Cat. No.99CH36349)

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The authors present a multiplication algorithm for low power implementation of digital filters on CMOS based digital signal processing systems. The algorithm decomposes individual coefficients into two primitive sub-components. The decomposition, performed using a heuristic approach, divides a given coefficient such that a part is produced which can be implemented using a single shift operation leaving another part with a reduced wordlength to be applied to the coefficient input of the hardware multiplier. This results in a significant reduction in the amount of switched capacitance and consequently power consumption. The algorithm has been used with a number of practical FIR filter examples achieving up to 63% saving in power. Results are provided which illustrate the effect of the algorithm on the amount of switched capacitance for different size multipliers. The paper provides a description of the algorithm, the evaluation procedure used, and associated results including overheads due to shift operations.

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