Germanium on Insulator Fabrication for Monolithic 3-D Integration

Abedin, Ahmad; Žurauskaitė, Laura; Asadollahi, Ali; Garidis, Konstantinos; Jayakumar, Ganesh; Malm, B. Gunnar; Hellström, Per‐Erik; Östling, Mikael

doi:10.1109/jeds.2018.2801335

Cited by 8 publications

(6 citation statements)

References 17 publications

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“…This is important not only for Ge CMOS aimed at high‐performance transistors, [ 26 ] but also for multi‐functional Ge devices built on the upper layer of a monolithic 3D integration. [ 56 ] As a demonstration, a large‐area Al/Ge diode array with uniform performances was fabricated in room temperature. After transferring a 14‐nm‐thick CNT film on to a 2‐in.…”

Section: Resultsmentioning

confidence: 99%

Fermi‐Level Depinning in Metal/Ge Junctions by Inserting a Carbon Nanotube Layer

Wei

Zhang

et al. 2022

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Germanium (Ge)‐based devices are recognized as one of the most promising next‐generation technologies for extending Moore's law. However, one of the critical issues is Fermi‐level pinning (FLP) at the metal/n‐Ge interface, and the resulting large contact resistance seriously degrades their performance. The insertion of a thin layer is one main technique for FLP modulation; however, the contact resistance is still limited by the remaining barrier height and the resistance induced by the insertion layer. In addition, the proposed depinning mechanisms are also controversial. Here, the authors report a wafer‐scale carbon nanotube (CNT) insertion method to alleviate FLP. The inserted conductive film reduces the effective Schottky barrier height without inducing a large resistance, leading to ohmic contact and the smallest contact resistance between a metal and a lightly doped n‐Ge. These devices also indicate that the metal‐induced gap states mechanism is responsible for the pinning. Based on the proposed technology, a wafer‐scale planar diode array is fabricated at room temperature without using the traditional ion‐implantation and annealing technology, achieving an on‐to‐off current ratio of 4.59 × 104. This work provides a new way of FLP modulation that helps to improve device performance with new materials.

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Section: Resultsmentioning

confidence: 99%

Fermi‐Level Depinning in Metal/Ge Junctions by Inserting a Carbon Nanotube Layer

Wei

Zhang

et al. 2022

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“…This achievement is a major result from the project allowing research on Ge transistor in the upper tiers with relevant channel thickness for sequential 3D integration. Details of the work are contained in the PhD thesis by A. Asadollahi (15) and in the PhD thesis by A. Abedin (16). The optimized process consists of growth of a 2 µm thick strained-relaxed Ge buffer, an epitaxial 10 nm Si0.5Ge0.5 etch stop and an epitaxial 25 nm thin Ge channel layer.…”

Section: Single Crystalline Ge Channel Materialsmentioning

confidence: 99%

“…After substantial optimization of the interfacial layer/ high-k stack, state-of-the-art interface state densities (Dit) in the low 10 11 eV -1 cm -2 range. This process was also used to fabricate fully depleted Ge devices (24,25). Although the interface state density is adequate for transistors, there is still an issue with charging/discharging of oxide traps leading to threshold voltage instabilities that are not compatible with high performance CMOS devices.…”

Section: High Performance Gate Dielectrics On Gementioning

confidence: 99%

(Invited) Sequential 3D Integration of Ge Transistors on Si CMOS

Ostling,

Hellstrom

2023

ECS Trans.

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To keep the scaling progress going, we must go three dimensional (3D). This paper outlines some technology challenges and solutions to integrate Ge p-type MOSFETs sequentially on Si CMOS. Such a solution addresses the grand challenge to enable increased device density. However, the device itself does not have to scale but at the same time innovative solutions are suggested for low supply voltage operation enabling energy efficient integrated circuits (ICs) that will not be dominated by energy consumption in interconnects. By stacking the transistors on top of each other, and connecting them with inter-tier via, the density of transistors per unit area increases. This approach demands that transistors are fabricated at a lower temperature than today’s Si CMOS technology. Here, we have focused on Ge based transistors, which have an inherently lower process temperature compared to Si transistors. Several technological and design breakthroughs towards realizing Ge based sequential 3D circuits are discussed.

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“…Compared to the conventional standard process, low-temperature processes using approximately 650 °C have been developed, improving the performance of M3DI [ 11 , 12 , 13 ]. Currently, most M3DI devices have been researched based on metal-oxide-semiconductor field-effect transistors (MOSFETs) that use Si, Ge, and III-V materials [ 14 , 15 , 16 , 17 ]. For the majority of MOSFETs, a thermal budget is required for dopant activation after the implantation process; however, there are physical limitations for using these as low-power devices.…”

Section: Introductionmentioning

confidence: 99%

Circuit Simulation Considering Electrical Coupling in Monolithic 3D Logics with Junctionless FETs

Ahn

2020

Micromachines

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The junctionless field-effect transistor (JLFET) compact model using the model parameters extracted from the LETI-UTSOI (version 2.1) model was proposed to perform circuit simulation considering the electrical coupling between the stacked JLFETs of a monolithic 3D integrated circuit (M3DIC) composed of JLFETs (M3DIC-JLFET). We validated the model by extracting the model parameters and comparing the simulation results of the technology computer-aided design and the Synopsys HSPICE circuit simulator. The performance of the M3DIC-JLFET was compared with that of the M3DIC composed of MOSFETs (M3DIC-MOSFET). The performance of a fan-out-3 ring oscillator with M3DIC-JLFET varied by less than 3% compared to that with M3DIC-MOSFET. The performances of ring oscillators of M3DIC-JLFET and M3DIC-MOSFET were almost the same. We simulated the performances of M3DICs such as an inverter, a NAND, a NOR, a 2 × 1 multiplexer, and a D flip-flop. The overall performance of the M3DIC-MOSFET was slightly better than that of the M3DIC-JLFET.

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Germanium on Insulator Fabrication for Monolithic 3-D Integration

Cited by 8 publications

References 17 publications

Fermi‐Level Depinning in Metal/Ge Junctions by Inserting a Carbon Nanotube Layer

Fermi‐Level Depinning in Metal/Ge Junctions by Inserting a Carbon Nanotube Layer

(Invited) Sequential 3D Integration of Ge Transistors on Si CMOS

Circuit Simulation Considering Electrical Coupling in Monolithic 3D Logics with Junctionless FETs

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