GFET Asymmetric Transfer Response Analysis through Access Region Resistances

Toral‐Lopez, Alejandro; Marín, Enrique G.; Pasadas, Francisco; Gonzalez-Medina, J. M.; Ruiz, Francisco G.; Jiménez, David; Godoy, A.

doi:10.3390/nano9071027

Cited by 11 publications

(10 citation statements)

References 36 publications

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“…The different slope of the two branches corresponds to the hole mobility (~--V s 150 cm 2 1 1 ) higher than the electron one (~--V s 100 cm 2 1 1 ), while the slight shift of the Dirac point to positive V gs indicates a low p-type carrier concentration due to adsorbates and process residues such as PMMA, not removed by the 1 mbar vacuum and 400 K annealing [59,84]. The holeelectron asymmetry is due to both unbalanced carrier injection from metal contacts and graphene interaction with the SiO 2 dielectric [84][85][86][87][88][89]. The interaction with SiO 2 is also the main cause of the hysteresis which appears when the gate voltage is swept back and forth [88][89][90].…”

Section: Resultsmentioning

confidence: 98%

Contact resistance and mobility in back-gate graphene transistors

et al. 2020

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The metal-graphene contact resistance is one of the major limiting factors toward the technological exploitation of graphene in electronic devices and sensors. High contact resistance can be detrimental to device performance and spoil the intrinsic great properties of graphene. In this paper, we fabricate back-gate graphene field-effect transistors with different geometries to study the contact and channel resistance as well as the carrier mobility as a function of gate voltage and temperature. We apply the transfer length method and the y-function method showing that the two approaches can complement each other to evaluate the contact resistance and prevent artifacts in the estimation of carrier mobility dependence on the gate-voltage. We find that the gate voltage modulates both the contact and the channel resistance in a similar way but does not change the carrier mobility. We also show that raising the temperature lowers the carrier mobility, has a negligible effect on the contact resistance, and can induce a transition from a semiconducting to a metallic behavior of the graphene sheet resistance, depending on the applied gate voltage. Finally, we show that eliminating the detrimental effects of the contact resistance on the transistor channel current almost doubles the carrier field-effect mobility and that a competitive contact resistance as low as 700 Ω·μm can be achieved by the zig-zag shaping of the Ni contact.

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Section: Resultsmentioning

confidence: 98%

Contact resistance and mobility in back-gate graphene transistors

et al. 2020

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“…Figure 1a shows the equivalent resistive networks of both three-and four-terminal GFETs with the intrinsic graphene channel resistance (Rch) and the extrinsic drain (Rc,d) and source (Rc,s) resistances. These include the drain and source metal-graphene contact resistances, respectively, which are currently crucial and undesirable elements impacting the RF performance of GFETs [43][44][45][46][47][48][49][50][51][52]. For the sake of simplicity, bias-independent contact resistances have been considered in the device modeling approach of this work.…”

Section: Dirac Point Shift (Dps): Theory Vs Experimentsmentioning

confidence: 99%

Unveiling the impact of the bias-dependent charge neutrality point on graphene based multi-transistor applications

et al. 2021

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The Dirac voltage of a graphene field-effect transistor (GFET) stands for the gate bias that sets the charge neutrality condition in the channel, thus resulting in a minimum conductivity. Controlling its dependence on the terminal biases is crucial for the design and optimization of radio-frequency applications based on multiple GFETs. However, the previous analysis of such dependence carried out for single devices is uncomplete and if not properly understood could result in circuit designs with poor performance. The control of the Dirac point shift (DPS) is particularly important for the deployment of graphene-based differential circuit topologies where keeping a strict symmetry between the electrically balanced branches is essential for exploiting the advantages of such topologies. This note sheds light on the impact of terminal biases on the DPS in a real device and sets a rigorous methodology to control it so to eventually optimize and exploit the performance of radio-frequency applications based on GFETs.

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“…Remarkably, at this bias point the resistance associated with the access regions (as computed from the self-consistent simulations), have comparable values to R c , reaching R s,acc = 3.3 kΩ • µm and R d,acc = 3.1 kΩ • µm at the source and drain ends, respectively and being rather bias dependent. This point highlights the strong impact that these gate-underlapped areas can produce on the RF performance of the device [31].…”

Section: Resultsmentioning

confidence: 94%