Global Modeling Strategy of Parasitic Coupled Currents Induced by Minority-Carrier Propagation in Semiconductor Substrates

Conte, Fabrizio Lo; Sallèse, Jean-Michel; Pastre, Marc; Krummenacher, F.; Kayal, Maher

doi:10.1109/ted.2009.2035025

Cited by 34 publications

(10 citation statements)

References 8 publications

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“…(d) A cell in the vertex of 3D matrix will generate only three of them. Technologically, only three parasitic components can be extracted: the EPFL enhanced diode [12], [13], the EPFL enhanced resistors [12], [13] and the homo-junction contacts [9]. the type of component to extract is determined by the doping types of two neighbouring cuboids, as shown in figure 7, either to be a resistor (same doping type) or to be a diode (different doping type).…”

Section: Three-dimensional Schematic Extractionmentioning

confidence: 99%

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A novel CAD framework for substrate modeling

Zeng¹,

Moursy²,

Iskander³

et al. 2014

2014 10th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)

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International audience—This paper presents a novel Computer-Aided-Design (CAD) framework for 3D extraction of the substrate electrical network. The proposed CAD tool (framework) models effi-ciently the minority carrier propagation inside substrate network especially for smart power ICs. Today, the minority carrier propagation into the substrate is ignored in existing SPICE simulators. It can be simulated using finite element methods in TCAD. Generally, TCAD simulations are accurates but take long time. Thus, they become of limited help for large scale ICs involving hundreds of transistors. In the context of the FP7 AUTOMICS project, the extraction tool will take into consideration the minority carriers effects. It will allow the designer to predict the minority carrier propagation through the substrate. This can be useful in evaluation the efficiency of ESD protection and latchup faults due to this leackage current in the substrate specially in HV/HT applications. With the proposed substrate network, the three-dimensional layout parasitics are constructed and substrate noise is simulated before first silicon fabrication. A simple diode example is illustrated to demonstrate the principal idea of the extraction tool

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Section: Three-dimensional Schematic Extractionmentioning

confidence: 99%

“…We present the modeling of the substrate by a three-dimensional extraction of enhanced resistors and diodes that has been presented in [12], [13]. Pattern based extraction strategies with intelligent computation algorithms are employed, for the purpose of delivering highly accurate, efficient and simple tool.…”

Section: Introductionmentioning

confidence: 99%

A novel CAD framework for substrate modeling

Zeng¹,

Moursy²,

Iskander³

et al. 2014

2014 10th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)

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show abstract

“…Standard industrial design flows do not take into account the minority carriers propagation in the substrate which is hard to model [2]. Technology Computer-Aided-Design (TCAD) tools [3] are considered as a powerful software to model the parasitic substrate coupling effect.…”

Section: Introductionmentioning

confidence: 99%

A CAD integrated solution of substrate modeling for industrial IC design

Zeng

Moursy

Iskander

et al. 2015

2015 IEEE 20th International Mixed-Signals Testing Workshop (IMSTW)

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Smart Power IC integrating high voltage devices with low voltage control blocks becomes more and more popular in automotive industry recently. Minority carriers injected into the substrate during switching of high power stages cause malfunction of sensitive nearby low voltage devices. Sometimes this may be destructive due to the presence of triggered latch up. The minority carriers propagation is extremely hard to model and difficult to predict using existing commercial standard design flow. In this paper, we propose a Computer-Aided-Design solution to characterise the substrate vertical and lateral parasitic for Smart Power IC in automotive applications. Investigation of complex benchmark structures is presented. SPICE simulations are performed for extracted 3D substrate netlist and compared to measurements. Good fitting between simulation and measurement validates the effectiveness and accuracy of the proposed CAD tool.

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“…The EPFL Substrate Model has been developed to enable the simulation of the injection of minority carriers as well as its propagation in the substrate with spice-like simulators [6]. This solution reduces the simulation time when compared to TCAD.…”

Section: Introductionmentioning

confidence: 99%

Optimization strategy of numerical simulations applied to EPFL substrate model

Stefanucci

Buccella

Kayal

et al. 2014

2014 Proceedings of the 21st International Conference Mixed Design of Integrated Circuits and Systems (MIXDES)

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A new methodology for modeling minority carriers diffusion in Smart Power ICs substrate using standard circuit simulators has been proposed by EPFL. For this purpose, a parasitic substrate network consisting of lumped elements is extracted from the circuit layout following a given substrate meshing strategy. In this work Design of Experiments (DOE) techniques are used to run a limited number of simulations to evaluate the influence of the meshing on the accuracy of the EPFL Substrate Model when compared to finite element simulations. A two-dimensional case study on a parasitic lateral bipolar is then proposed with both spice-like and finite element simulation results for the minority carriers diffusion. A linear model is developed to estimate the most important geometrical domains influencing the accuracy of the studied model.

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Global Modeling Strategy of Parasitic Coupled Currents Induced by Minority-Carrier Propagation in Semiconductor Substrates

Cited by 34 publications

References 8 publications

A novel CAD framework for substrate modeling

A novel CAD framework for substrate modeling

A CAD integrated solution of substrate modeling for industrial IC design

Optimization strategy of numerical simulations applied to EPFL substrate model

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