Twelfth Annual IEEE International ASIC/SOC Conference (Cat. No.99TH8454)
DOI: 10.1109/asic.1999.806526
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Globally-asynchronous locally-synchronous architectures to simplify the design of on-chip systems

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Cited by 80 publications
(65 citation statements)
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“…These concerns can be generally attributed to data and system safety issues. Although the simulations and tests reported in [8] and [9] show that their design works properly, such simulations and tests can only cover a small fraction of all possible configurations of relative delays in asynchronous communication, while we find that various malfunctions may still emerge under different relative delays. Applying formal verification, we find the potential pitfalls and provide delay constraints that permit to size the circuits so that the pitfalls are avoided.…”
Section: Introductionmentioning
confidence: 99%
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“…These concerns can be generally attributed to data and system safety issues. Although the simulations and tests reported in [8] and [9] show that their design works properly, such simulations and tests can only cover a small fraction of all possible configurations of relative delays in asynchronous communication, while we find that various malfunctions may still emerge under different relative delays. Applying formal verification, we find the potential pitfalls and provide delay constraints that permit to size the circuits so that the pitfalls are avoided.…”
Section: Introductionmentioning
confidence: 99%
“…In this paper, we: 1) propose new data transition model to represent the implicit relationship between clock and data validity events; 2) construct comprehensive implementation models for the asynchronous wrapper and the asynchronous communication scheme; 3) report several design pitfalls, including hazards in a design, obtained from 3D synthesizing tool, which claimed by [9] to be hazard-free; 4) provide relative timing constraints that were not mentioned by [8] and [9], along with fault diagnosis which indicates that the disregard of these constraints can cause system deadlock or erroneous data transfers.…”
Section: Introductionmentioning
confidence: 99%
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“…This is not the first GALS interface to have been designed. Examples of others are found in [4] and [5]. The most important difference between the interface presented here and others in the literature is that this one does not require the interface to control the local clock signals, whereas the others require a "stoppable clock".…”
Section: Gals Interfacementioning
confidence: 95%