Globally optimal time-multiplexing in inter-FPGA connections for accelerating multi-FPGA systems

Inagi, Masato; Takashima, Yoshinori; Nakamura, Yūichi

doi:10.1109/fpl.2009.5272309

Cited by 30 publications

(10 citation statements)

References 7 publications

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“…The paper [8] presents an architecture for this purpose, and the work [9] proposes a solution for optimizing communication between different FPGA devices.…”

Section: Related Workmentioning

confidence: 99%

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An inter-FPGA communication bus with error detection and dynamic clock phase adjustment

et al. 2015

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Background: Nowadays, systems involving multiple FPGAs are used for various scientific applications. Such systems require a data bus dedicated to the communication between FPGAs, which could be done through a LVDS type. Another important factor is that the routing that interconnects the LVDS pins on the platform should be precisely developed to avoid instabilities in communication. Unfortunately, many platforms available in the market do not observe such restrictions, limiting the throughput of the bus. Methods: This paper presents an inter-FPGAs communication channel based on a DDR interface directed to this kind of platform. This approach promotes a stable communication between these devices without the use of LVDS pins. An error detection module was also designed to ensure the sending integrity and correct any errors on the bus. A mechanism for dynamic and automatic clock phase adjustment used on the bus was also implemented to ensure that the developed modules were compatible with other platforms. Results: The channel has been implemented in a PROCStarIII platform and rates of 4.76 Gbps were achieved. Conclusions: The channel has been validated on a commercial platform with success and the synthesis results, as well as the performance results obtained by using it in a real implementation of the RTM algorithm, are also presented.

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“…The paper [8] presents an architecture for this purpose, and the work [9] proposes a solution for optimizing communication between different FPGA devices.…”

Section: Related Workmentioning

confidence: 99%

“…In [9], a solution for optimizing inter-FPGA communication using channel adaptation is shown. The work demonstrates that each platform has its own characteristics, and to migrate up the project to another platform, you often need to change the architecture to adapt to necessary changes.…”

Section: Related Workmentioning

confidence: 99%

An inter-FPGA communication bus with error detection and dynamic clock phase adjustment

et al. 2015

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“…An iterative routing algorithm is used to route the inter-FPGA signal and, for exceeding signal cases the multiplexing IPs are implemented in sending and receiving FPGA to transmit the signal through the same physical wire. In [12], a new approach is proposed using routability-driven routing approach which gives a better result than approach used in [10]. In [13], a proposed iterative routing algorithm in [14] is enhanced to route multi-terminal nets in multi-point tracks for routing cut nets in two point track by saving the FPGA [15], author has present partitioning method based on topological ordering and levelization.…”

Section: Literature Reviewmentioning

confidence: 99%

Manual clock distribution technique in partitioning stage for multi-FPGA prototyping

Savugathali

Mustapa

Zakaria

2019

IJEECS

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<span>As the complexity of ASIC/SoC design is increasing along with the number of logic gates, a prototyping process in the verification stage is facing a challenge when the ASIC/SoC design cannot fit into a single FPGA. A solution to prototyping multi-million logic gates of ASIC/SoC circuit into the FPGA platform for verification purpose is by partition the design into multi-FPGA. There are various <a name="_Hlk509759576"></a>implementation tools and platform available in the market which automates an FPGA-based prototype phase such as Cadence Protium Rapid Prototyping Platform, Synopsys and S2C. In this paper, <a name="_Hlk509759525"></a>Synopsys protocompiler tool will be used to perform the prototyping process of the large 4 core CPU based circuit into the HAPS-80 FPGA platform. This paper will be focusing on the partition requirement needed to successfully prototype the large SoC circuit into the multi-FPGA. The presence of cut clocks in a circuit after partition stage will resulting to the failure in routing stage due to the congestion error. In this paper, two techniques are used, which is automatic clock replication by the Synopsys Protocompiler tool and our proposed technique which is Manual Clock Distribution technique to solve the presence of the cut clock, so that the circuit is able to meet the partition requirement to complete the prototyping process into multi-FPGA. Obtained result from the proposed technique showing that prototyping the large SoC circuit into the multi-FPGA platform has met the specification by eliminating 100% presence of cut clock.</span>

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“…Different approaches have been presented in the past for inter-FPGA routing. For example, an obstacle avoidance inter-FPGA routing approach based on integer linear programming is presented in [22]. This technique generates good routing results in a short time.…”

Section: Related Workmentioning

confidence: 99%

“…This problem is tackled in [23] where authors propose a negotiation based, congestion-driven inter-FPGA routing technique. This technique, however, takes more time as compared to [22] to find a feasible solution. When a benchmark is partitioned into multiple parts, the resulting cut-nets can be either two terminal (having single source and single destination) or they can be multi terminal (having single source and multiple destinations).…”

Section: Related Workmentioning

confidence: 99%

Inter-FPGA interconnect topologies exploration for multi-FPGA systems

Farooq

Mehrez

Bhatti

2018

Des Autom Embed Syst

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Prototyping using multi-FPGA systems offers significant advantages over simulation and emulation based pre-silicon verification techniques. Multi-FPGA prototyping follows a complex design flow where the quality of associated tools and the architecture of interconnect topology play a very important role in the performance of final prototyped design. A well designed interconnect topology may remain underutilized because of a poor routing tool and vice versa. This makes the selection of a good routing tool and the exploration of interconnect topologies extremely important for the quality of final design. In this work, we present a detailed comparison between six inter-FPGA interconnect topologies. We present a generic routing tool and for each topology, ten large, complex benchmarks are prototyped on four FPGA boards using this tool. Experimentation reveals that fully customized interconnect topology using a hybrid combination of direct two and multi point tracks gives the best frequency results for all the FPGA boards. On average, this topology gives 26.2, 28.5, 9.5, 32.1 and 12.4% better frequency results as compared to five other interconnect topologies. We also perform routing time comparison and the topology using generic hybrid combination of direct two and multi point tracks gives the best results. On average, this topology produces 1.8×, 2×, 2×, 9.2×, and 4.4× better results as compared to five other topologies under consideration. Frequency-time tradeoff analysis along with flexibility and setup time of different topologies is also performed. It reveals that a partially customized topology with hybrid combination of direct two and multi point tracks gives the best frequency-time tradeoff for smaller FPGA boards while a partially customized topology B Umer Farooq 123 118 U. Farooq et al.with switch-based and multi point connections gives the best results for larger FPGA boards with reasonable flexibility and moderate setup time.

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Globally optimal time-multiplexing in inter-FPGA connections for accelerating multi-FPGA systems

Cited by 30 publications

References 7 publications

An inter-FPGA communication bus with error detection and dynamic clock phase adjustment

An inter-FPGA communication bus with error detection and dynamic clock phase adjustment

Manual clock distribution technique in partitioning stage for multi-FPGA prototyping

Inter-FPGA interconnect topologies exploration for multi-FPGA systems

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