Goal-oriented stimulus generation for analog circuits

Ahmadyan, Seyed Nematollah; Kumar, Jayanand Asok; Vasudevan, Shobha

doi:10.1145/2228360.2228544

Cited by 17 publications

(9 citation statements)

References 12 publications

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“…For example (s [3], s [7], s [11] , s [15]···) would be a new sample We use the circuits in Figure 2 to show the results of the equidistant compressional method, and assign normal and faulty parameters to the components in Figure 2 to build normal and faulty circuit instances. All the parameters fall inside their respective ranges of tolerance in normal circuit.…”

Section: Compression Of the Sample Space 31 Equidistant Compressionmentioning

confidence: 99%

Test Generation Algorithm Based on SVM with compressing Sample Space Methods

2015

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Fault detection and classification in this paper are based on a Support Vector Machine (SVM), so that the response vectors of normal and faulty circuits can be distinguished on the basis of nonlinear classification. SVM [15], [16] is to classify small samples based on statistical learning theory. This method has proven adept at dealing with highly nonlinear classification problems. The rule-less response data sampled from electronic systems are an excellent example. When the bandwidth of the DUT is much smaller than the sampling frequency of the DAC/ADC, the sample vectors of the impulse-response become quite large. The response data of the sample space contains redundant data, because successive impulse-response samples may get quite close. The redundancy will waste the needless computational load. In this paper we propose a maximal difference method to compress the sample space, and reduce computational load.

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Section: Compression Of the Sample Space 31 Equidistant Compressionmentioning

confidence: 99%

Test Generation Algorithm Based on SVM with compressing Sample Space Methods

2015

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“…Dang et al [24] used motion planning techniques for rapidlyexploring random trees (RRTs) to verify specifications of analog circuits. Ahmadyan et al [25] also used RRTs to generate property-oriented test cases for analog circuits.…”

Section: A Related Workmentioning

confidence: 99%

From statistical model checking to statistical model inference: Characterizing the effect of process variations in analog circuits

Zhang

Sankaranarayanan

Somenzi

et al. 2013

2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

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This paper studies the effect of parameter variation on the behavior of analog circuits at the transistor (netlist) level. It is well known that variation in key circuit parameters can often adversely impact the correctness and performance of analog circuits during fabrication. An important problem lies in characterizing a safe subset of the parameter space for which the circuit can be guaranteed to satisfy the design specification. Due to the sheer size and complexity of analog circuits, a formal approach to the problem remains out of reach, especially at the transistor level. Therefore, we present a statistical model inference approach that exploits recent advances in statistical verification techniques. Our approach uses extensive circuit simulations to infer polynomials that approximate the behavior of a circuit. A procedure inspired by statistical model checking is then introduced to produce "statistically sound" models that extend the polynomial approximation. The resulting model can be viewed as a statistically guaranteed over-approximation of the circuit behavior. The proposed technique is demonstrated with two case studies in which it identifies subsets of parameters that satisfy the design specifications.

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“…Statistical techniques have been proposed to find parametric faults such as the Gibbs sampling technique for SRAMs [11] or to develop stimuli for analog circuits to find unique output responses [12]. However, these approaches need significant number of simulations even for examples with small dimensions.…”

Section: Past Work and Contribution Of This Papermentioning

confidence: 99%

Scalable and efficient analog parametric fault identification

Yelten

Natarajan

Xue

et al. 2013

2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

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Analog circuits embedded in large mixed-signal designs can fail due to unexpected process parameter excursions. To evaluate manufacturing tests in terms of their ability to detect such failures, parametric faults leading to circuit failures should be identified. This paper proposes an iterative sampling method to identify these faults in largescale analog circuits with a constrained simulation budget. Experiment results on two circuits from a serial IO interface demonstrate the effectiveness of the methodology. The proposed method identifies a significantly larger and diverse set of critical parametric faults compared to a Monte Carlobased approach for identical computational budget, particularly for cases involving significant process variations. Keywords-test coverage; within-die variations; parametric faults; process variations; analog circuits; design for test.I.

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Goal-oriented stimulus generation for analog circuits

Cited by 17 publications

References 12 publications

Test Generation Algorithm Based on SVM with compressing Sample Space Methods

Test Generation Algorithm Based on SVM with compressing Sample Space Methods

From statistical model checking to statistical model inference: Characterizing the effect of process variations in analog circuits

Scalable and efficient analog parametric fault identification

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