Graphene tunneling FET and its applications in low-power circuit design

Yang, Xuebei; Chauhan, Jyotsna; Guo, Jing; Mohanram, Kartik

doi:10.1145/1785481.1785544

Cited by 14 publications

(9 citation statements)

References 15 publications

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“…3b, which is measured from the input-output switching characteristics of an inverter at a 90% point. We obtained ~145 ps delay, which is much smaller than the earlier work reported [14]. The slope of DC input-output characteristics of the inverter, shown in Fig.…”

Section: Mos2 Tfet Inverter Design and Performance Evaluationcontrasting

confidence: 56%

Modeling of MoS2 Tunnel Field Effect Transistor in Verilog-A for VLSI Circuit Design

Adesina

Srivast

et al. 2021

Preprint

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This paper presents a newly designed physics-based analytical current transport model of both n- and p-type MoS2 tunnel field-effect transistor (TFET) using a high-level hardware language Verilog-Analog (Verilog-A) within Cadence/Spectre. The performance of our model is analysed by extracting different parameters, including transfer characteristics, power dissipation, and consumption, delay, power delay product (PDP) from the designed inverter. Moreover, we design a ring oscillator, and a half adder circuit to assess the compatibility of our model in both the analog and digital circuits. Our observation reveals that the voltage-controlled oscillator (VCO) can operate at a frequency of 31.6 GHz with a power consumption of 0.083 mW, and generates a phase noise of -122.5 dBc/Hz at 1MHz offset frequency. The simulated outputs (sum & carry) obtained from the half adder circuit exactly match the truth table of the circuit. Last, we present a comparison, using the performance parameters, of the ring oscillator with existing CMOS and GFET technologies. The results show that our designed VCO oscillates at a higher frequency with low power consumption and improved phase noise performance. With all the output characteristics obtained from the commercial software simulation, we expect our model to be applicable to a real-time low power VLSI circuit.

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Section: Mos2 Tfet Inverter Design and Performance Evaluationcontrasting

confidence: 56%

Modeling of MoS2 Tunnel Field Effect Transistor in Verilog-A for VLSI Circuit Design

Adesina

Srivast

et al. 2021

Preprint

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“…A detailed discussion of these simulation techniques are out of the scope of this work and we refer to Datta [2005] and Lundstrom and Guo [2006] for an extensive discussion on this topic. These simulation techniques have been shown to provide excellent agreement to experimental measurements on fabricated devices for other emerging devices [Choudhury et al 2008;Yang et al 2010;Yang and Mohanram 2011]. The device simulations provide…”

Section: Circuit Simulation and Designmentioning

confidence: 69%

“…Since there are no compact models for TMDCFETs and BPFETs available presently, we built a lookup table-based Verilog-A model of the TMDCFET and the BPFET for high-level circuit simulation of SRAMs using Cadence Spectre. These Verilog-A models characterize both the DC and the transient behavior of the transistors using first-order current-voltage-charge differential equations This method is suitable for accurately and efficiently modeling these emerging devices, and has been used in studying other emerging devices (e.g., Singh et al [2010], Yang and Mohanram [2011], Choudhury et al [2008], and Yang et al [2010]). Atomistic self-consistent device simulation techniques have been adopted to simulate the intrinsic TMDCFETs and BPFETs in this article.…”

Section: Circuit Simulation and Designmentioning

confidence: 99%

Monolayer Transistor SRAMs

Rakshit

Mohanram

Wan

et al. 2017

J. Emerg. Technol. Comput. Syst.

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Monolayer heterojunction FETs based on vertical heterogeneous transition metal dichalcogenides (TMD-CFETs) and planar black phosphorus FETs (BPFETs) have demonstrated excellent subthreshold swing, high I ON /I OFF , and high scalability, making them attractive candidates for post-CMOS memory design. This article explores TMDCFET and BPFET SRAM design by combining atomistic self-consistent device modeling with SRAM circuit design and simulation. We perform detailed evaluations of the TMDCFET/BPFET SRAMs at a single bitcell and at SRAM array level. Our simulations show that at low operating voltages, TMDCFET/BPFET SRAMs exhibit significant advantages in static power, dynamic read/write noise margin, and read/write delay over nominal 16nm CMOS SRAMs at both bitcell and array-level implementations. We also analyze the effect of process variations on the performance of TMDCFET/BPFET SRAMs. Our simulations demonstrate that TMDCFET/BPFET SRAMs exhibit high tolerance to process variations, which is desirable for low operating voltages.

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“…Compared to GNRFETs, GNRTFETs benefit of superior gate control and higher I ON current, and thus seems to be more attractive then GNRFETs for graphene-based computing. To get inside in GNRTFETs potential performance we present in Table II the evaluation results reported in [21] for a low-power inverter constructed with double-gated GNRTFETs with GNR channel widths of 10a, 13a, and 16a. One can observe in the Table that the GNRTFET avenue enables 8 to 9 orders of magnitude reduction of the static power when compared to the GNRFET counterpart.…”

Section: B Gnr-based Tunelling Fetsmentioning

confidence: 99%

“…To this end we describe Graphene Nanoribbon (GNR) based field Effect Transistors (FETs) and their underlying operation principle [18] and tunnelling GNR based FETs [19]. To put things into prospective we also summarize the potential performance of Boolean gates based on such graphene switches as reported in [20] and [21].…”

Section: Introductionmentioning

confidence: 99%

On Effective Graphene Based Computing

Laurenciu

Cotofana

2018

2018 International Semiconductor Conference (CAS)

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With CMOS feature size heading towards atomic dimensions, unjustifiable static power, reliability, and economic implications are exacerbating, prompting for research on new materials, devices, and/or computation paradigms. Within this context, Graphene Nanoribbons (GNRs), owing to graphene's excellent electronic properties, may serve as basic blocks for carbon-based nanoelectronics. In this paper, we present the two main avenues, i.e., graphene FET-and GNR-based, undertaken towards graphene based computing. The first approach is conservative and focuses on the realization of graphene FET transistor based switches as MOSFET replacements to maintain the state of the art logic Boolean algebra paradigm design methodology. The second one follows a different line of thinking and seeks GNR-based structures able to provide more complex behaviours by making better use of graphene's conduction properties. We first discuss Graphene Nanoribbon (GNR) based field Effect Transistors (GNRFETs) and Tunnelling GNR based Transistors (GNRTFETs) and their utilization as underlying elements for Boolean gate implementations. Subsequently, we present GNRbased structures that can directly compute Boolean functions, e.g., NAND, XOR, by means of one GNR only and a way to complementary arrange them in energy effective gates. To get inside into the potential of the two avenues we consider an inverter as discussion vehicle and evaluate the designs in terms of area and energy consumption. The GNR-based structure outperforms its counterparts by 15× up to 104× and 230× smaller delay and 6 to 7 and 4 orders of magnitude smaller power than the GNRFETand GNRTFET-based designs, respectively. Moreover, when compared with CMOS 7 nm Boolean gates GNR-based desgns exhibit up to 6× smaller delay, and up to 2 orders of magnitude smaller active area, and total power consumption. Our analysis confirms that the alternative GNR-based design paradigm, which transcends the traditional switch based approach and takes better advantage of graphene intrinsicnproperties, is better suited for future carbon based nanoelectronics.

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Graphene tunneling FET and its applications in low-power circuit design

Cited by 14 publications

References 15 publications

Modeling of MoS2 Tunnel Field Effect Transistor in Verilog-A for VLSI Circuit Design

Modeling of MoS2 Tunnel Field Effect Transistor in Verilog-A for VLSI Circuit Design

Monolayer Transistor SRAMs

On Effective Graphene Based Computing

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