Graphene and hexagonal boron nitride (h-BN) have similar crystal structures with a lattice constant difference of only 2%. However, graphene is a zero-bandgap semiconductor with remarkably high carrier mobility at room temperature, whereas an atomically thin layer of h-BN is a dielectric with a wide bandgap of ∼5.9 eV. Accordingly, if precise two-dimensional domains of graphene and h-BN can be seamlessly stitched together, hybrid atomic layers with interesting electronic applications could be created. Here, we show that planar graphene/h-BN heterostructures can be formed by growing graphene in lithographically patterned h-BN atomic layers. Our approach can create periodic arrangements of domains with size ranging from tens of nanometres to millimetres. The resulting graphene/h-BN atomic layers can be peeled off the growth substrate and transferred to various platforms including flexible substrates. We also show that the technique can be used to fabricate two-dimensional devices, such as a split closed-loop resonator that works as a bandpass filter.

We propose and experimentally demonstrate a triple-mode single-transistor graphene amplifier utilizing a three-terminal back-gated single-layer graphene transistor. The ambipolar nature of electronic transport in graphene transistors leads to increased amplifier functionality as compared to amplifiers built with unipolar semiconductor devices. The ambipolar graphene transistors can be configured as n-type, p-type, or hybrid-type by changing the gate bias. As a result, the single-transistor graphene amplifier can operate in the common-source, common-drain, or frequency multiplication mode, respectively. This in-field controllability of the single-transistor graphene amplifier can be used to realize the modulation necessary for phase shift keying and frequency shift keying, which are widely used in wireless applications. It also offers new opportunities for designing analog circuits with simpler structure and higher integration densities for communications applications.

Abstract-We report the experimental demonstration of a multiplier phase detector implemented with a single top-gated graphene transistor. Ambipolar current conduction in graphene transistors enables simplification of the design of the multiplier phase detector and reduces its complexity in comparison to phase detectors based on conventional unipolar transistors. Fabrication of top-gated graphene transistors is essential to achieve the higher gain necessary to demonstrate phase detection. We report a phase detector gain of −7 mV/rad in this letter. An analysis of key technological parameters of the graphene transistor, including series resistance, top-gate insulator thickness, and output resistance, indicates that the phase detector gain can be improved by as much as two orders of magnitude.

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Graphene nanoribbon tunneling FETs (GNR TFETs) are promising devices for post-CMOS low-power applications because of the low subthreshold swing, high I on/Ioff, and potential for large scale processing and fabrication. This paper combines atomistic quantum transport modeling with circuit simulation to explore GNR TFET circuits for low-power applications. A quantitative study of the effects of variations on the performance and reliability of GNR TFET circuits is also presented. Simulation results indicate that GNR TFET circuits are extremely competitive in performance in comparison to conventional CMOS circuits at comparable operating points, with static power consumption that is lower by 8-9 orders of magnitude. It is also observed that GNR TFET circuits are susceptible to parameter variations, motivating engineering and design challenges to be addressed by the device and CAD communities.