Graphite-based heat spreaders for hotspot mitigation in 3D ICs

Santos, Carla Eliete Iochims dos; Prieto, R.; Vivet, Pascal; Colonna, Jean-Philippe; Coudrain, P.; Reis, Ricardo

doi:10.1109/3dic.2015.7334618

Cited by 4 publications

(5 citation statements)

References 8 publications

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“…Then the acceptor wafer was immersed in the water and slowly withdrawn, in which procedure the orientation of CNT/copolymer film was maintained by manual operation. (8) The acceptor wafer was then baked at a stepped temperature up to 120 C to entirely evaporate the water for 20 min. (9) The acceptor wafer was immersed in acetone to completely remove the copolymer on A-CNT film.…”

Section: Methodsmentioning

confidence: 99%

“…Since each layer is sequentially processed with interlayer dielectric (ILD) insulation and interlayer via (ILV) connection, M3D integration enables the alignment accuracy and feature size of both devices and ILVs to be scaled toward the sub-100 nm level. 8 Such high-density direct connection vias reduce the wire length and thickness of each layer, and the low-κ ILD layers lower the coupling parasitic capacitance of the adjacent layers, which contributes to suppressing the heat dissipation and RC delay. 9 In spite of some prototypes with an M3D architecture being demonstrated since 1987, the thermal budget issue hinders the growth of high-quality semiconductors and then high-performance transistors at upper layers, attributed to the temperature-compromised fabrication process.…”

Section: Introductionmentioning

confidence: 99%

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Monolithic three‐dimensional integration of aligned carbon nanotube transistors for high‐performance integrated circuits

Fan

Cheng

et al. 2023

InfoMat

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Carbon nanotube field‐effect transistors (CNT FETs) have been demonstrated to exhibit high performance only through low‐temperature fabrication process and require a low thermal budget to construct monolithic three‐dimensional (M3D) integrated circuits (ICs), which have been considered a promising technology to meet the demands of high‐bandwidth computing and fully functional integration. However, the lack of high‐quality CNT materials at the upper layer and a low‐parasitic interlayer dielectric (ILD) makes the reported M3D CNT FETs and ICs unable to provide the predicted high performance. In this work, we demonstrate a multilayer stackable process for M3D integration of high‐performance aligned carbon nanotube (A‐CNT) transistors and ICs. A low‐κ (~3) interlayer SiO2 layer is prepared from spin‐on‐glass (SOG) through processes with a highest temperature of 220°C, presenting low parasitic capacitance between two transistor layers and excellent planarization to offer an ideal surface for the A‐CNT and device fabrication process. A high‐quality A‐CNT film with a carrier mobility of 650 cm2 V–1 s–1 is prepared on the ILD layer through a clean transfer process, enabling the upper CNT FETs fabricated with a low‐temperature process to exhibit high on‐state current (1 mA μm–1) and peak transconductance (0.98 mS μm–1). The bottom A‐CNT FETs maintain pristine high performance after undergoing the ILD growth and upper FET fabrication. As a result, 5‐stage ring oscillators utilizing the M3D architecture show a gate propagation delay of 17 ps and an active region of approximately 100 μm2, representing the fastest and the most compact M3D ICs to date.

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Section: Methodsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Monolithic three‐dimensional integration of aligned carbon nanotube transistors for high‐performance integrated circuits

Fan

Cheng

et al. 2023

InfoMat

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“…The ability to construct three-dimensional circuits removes the fundamental constraint that the circuit graph be planar which afflicts two-dimensional circuits such as most CMOS-based designs. It should be noted that three-dimensional CMOS-based integrated circuits do exist; however, their practical use is generally limited to low-power applications due to heat dissipation issues [30]. The far greater theoretical efficiency of molecular mechanical logic gates would allow them to circumvent this limitation, potentially favoring three-dimensional molecular-mechanical logic circuits over two-dimensional circuits.…”

Section: Circuit Constructionmentioning

confidence: 99%

Simulation of reversible molecular mechanical logic gates and circuits

2023

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Landauer's principle places a fundamental lower limit on the work required to perform a logically irreversible operation. Logically reversible gates provide a way to avoid these work costs and also simplify the task of making the computation as a whole thermodynamically reversible. The inherent reversibility of mechanical logic gates would make them good candidates for the design of practical logically reversible computing systems if not for the relatively large size and mass of such systems. In this paper we outline the design and simulation of reversible molecular mechanical logic gates that come close to the limits of thermodynamic reversibility even under the effects of thermal noise, and outline associated circuit components from which arbitrary combinatorial reversible circuits can be constructed and simulated. We demonstrate that isolated components can be operated in a thermodynamically reversible manner, and explore the complexities of combining components to implement more complex computations. Finally, we demonstrate a method to construct arbitrarily large reversible combinatorial circuits using multiple external controls and signal boosters with a working half-adder circuit.

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“…Several researchers discuss about maximum temperature and temperature rise time of a hotspot on LSI with a thinned Si base, and they suggest that the thermal characteristics and thickness of Si base show trade-off relationships. [17][18][19][20][21] Some researchers analytically investigated thermal problems in 3DS-ICs, [22][23][24] arising from more complex trade-off relationship of performance with further downscaling and increased current density by stacking. As for the transient thermal characteristics of thinned LSI, only a few research studies have been carried out on the macroscopic scale.…”

Section: Introductionmentioning

confidence: 99%

“…[17][18][19][20][21] Some researchers analytically investigated thermal problems in 3DS-ICs, [22][23][24] arising from more complex trade-off relationship of performance with further downscaling and increased current density by stacking. As for the transient thermal characteristics of thinned LSI, only a few research studies have been carried out on the macroscopic scale.…”

Section: Introductionmentioning

confidence: 99%

Investigation of transient thermal dissipation in thinned LSI for advanced packaging

Araga¹,

Shimamoto²,

Melamed³

et al. 2018

Jpn. J. Appl. Phys.

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Thinning of LSI is necessary for superior form factor and performance in dense cutting-edge packaging technologies. At the same time, degradation of thermal characteristics caused by the steep thermal gradient on LSIs with thinned base silicon is a concern. To manage a thermal environment in advanced packages, thermal characteristics of the thinned LSIs must be clarified. In this study, static and dynamic thermal dissipations were analyzed before and after thinning silicon to determine variations of thermal characteristics in thinned LSI. Measurement results revealed that silicon thinning affects dynamic thermal characteristics as well as static one. The transient variations of thermal characteristics of thinned LSI are precisely verified by analysis using an equivalent model based on the thermal network method. The results of analysis suggest that transient thermal characteristics can be easily estimated by employing the equivalent model.

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Graphite-based heat spreaders for hotspot mitigation in 3D ICs

Cited by 4 publications

References 8 publications

Monolithic three‐dimensional integration of aligned carbon nanotube transistors for high‐performance integrated circuits

Monolithic three‐dimensional integration of aligned carbon nanotube transistors for high‐performance integrated circuits

Simulation of reversible molecular mechanical logic gates and circuits

Investigation of transient thermal dissipation in thinned LSI for advanced packaging

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