GROK-INT: Generating Real On-Chip Knowledge for Interconnect Delays Using Timing Extraction

Gojman, Benjamin; DeHon, André

doi:10.1109/fccm.2014.31

Cited by 18 publications

(19 citation statements)

References 10 publications

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“…RELATED WORK A notable example of FPGA self-characterization work is [5]; the level of precision is one of the finest published, with 500 consecutive measurements of a single path providing a standard deviation of 0.61 ps. Another notable work measured the delays of paths containing six or more LUTs and then estimated the delays of constituent paths; the repeatability of the estimates was 3.2 ps [6]. Several ot involved self-characterization but typically ha the measurement precision [7].…”

Section: • New Empirical Insight Into Burn-in Of Fpga Lut Contentsmentioning

confidence: 99%

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High-precision self-characterization for the LUT burn-in information leakage threat

Zick

French

2014

2014 24th International Conference on Field Programmable Logic and Applications (FPL)

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Information security in FPGAs is at risk; during system operation, data and usage patterns can potentially get imprinted into a chip's physical characteristics, allowing an attacker to later recover intellectual property or cryptographic secrets. Can "data burn-in" vulnerabilities in FPGAs be characterized at low cost? Specifically, can slight shifts in path delays due to burn-in be measured with enough precision? This paper contributes methods for self-characterization of delay changes using novel isolation of key FPGA transistors, improved clock sweeping, and enhanced estimation from launch-andcapture data. Hardware experiments on 2048 Xilinx Kintex-7 paths demonstrate measurement precision of 30-60 femtoseconds, which is more than 10× finer than previous selfcharacterization results. Further, results show that unintentional burn-in of FPGA LUT contents does indeed occur and can in some cases be detected within a single week, highlighting the need to deploy countermeasures.

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Section: • New Empirical Insight Into Burn-in Of Fpga Lut Contentsmentioning

confidence: 99%

“…Using a single source such as an controlled oscillator, two clocks are generat phase shift. As an example, Xilinx Kintexcan generate phase shifts of roughly 13 ps characterization of paths nearly 100× shorter t degree launch and capture is limited to paths ps in [6]). …”

Section: B Improvements To Test Architecturementioning

confidence: 99%

High-precision self-characterization for the LUT burn-in information leakage threat

Zick

French

2014

2014 24th International Conference on Field Programmable Logic and Applications (FPL)

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“…According to the prediction of increase in variation in future FPGAs [18], the stochastic component of the variation maps is amplified to an overall variation of σ/µ = 30%. We have tested 20 MCNC benchmarks circuits to investigate the potential improvement of our method under different designs and circuit structures.…”

Section: B Experiments Setupmentioning

confidence: 99%

“…In Fig. 4(a), N on Crit T is set to 20% of the 20 paths and therefore the 5 least critical paths (16)(17)(18)(19)(20) are released and rerouted.…”

Section: Execution Time Of Variation-aware Full Chipwise Routingmentioning

confidence: 99%

Exploiting stochastic delay variability on FPGAs with adaptive partial rerouting

Guan

Wong

Chaudhuri

et al. 2013

2013 International Conference on Field-Programmable Technology (FPT)

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Aggressive transistor scaling will soon lead us to the physical upper-bound of process technology, where stochastic process variability dominates the timing performance of FPGA components. In this paper, a variation-aware partial-rerouting method is proposed to mitigate and take advantage of the effect of delay variability due to process variation. The variation in logic delay across each FPGA (variation map) is measured on commercial FPGAs and is used to assess the effectiveness and potential gain of the proposed method on current FPGA architectures. Our partial-rerouting method achieved 5.25% improvement in critical path delay under a delay variability of σ/µ = 0.3, and is considerably less time consuming than using variation-aware full chipwise routing, which gave a slightly better timing gain of 6.41% but requires 8× more execution time when optimising for 100 target FPGAs with unique variation maps.

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“…In a practical situation, this may result in a large gap between the predicted frequency and the actual frequency under which the correct operation is maintained [18].…”

Section: Exploring the Conservative Timing Marginmentioning

confidence: 99%

Accuracy-Performance Tradeoffs on an FPGA through Overclocking

Shi

Boland

Constantinides

2013

2013 IEEE 21st Annual International Symposium on Field-Programmable Custom Computing Machines

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Abstract-Embedded applications can often demand stringent latency requirements. While high degrees of parallelism within custom FPGA-based accelerators may help to some extent, it may also be necessary to limit the precision used in the datapath to boost the operating frequency of the implementation. However, by reducing the precision, the engineer introduces quantization error into the design. In this paper, we demonstrate that for many applications it would be preferable to simply overclock the design and accept that timing violations may arise. Since the errors introduced by timing violations occur rarely, they will cause less noise than quantization errors. Through the use of analytical models and empirical results on a Xilinx Virtex-6 FPGA, we show that a geometric mean reduction of 67.9% to 98.8% in error expectation or a geometric mean improvement of 3.1% to 27.6% in operating frequency can be obtained using this alternative design methodology.

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GROK-INT: Generating Real On-Chip Knowledge for Interconnect Delays Using Timing Extraction

Cited by 18 publications

References 10 publications

High-precision self-characterization for the LUT burn-in information leakage threat

High-precision self-characterization for the LUT burn-in information leakage threat

Exploiting stochastic delay variability on FPGAs with adaptive partial rerouting

Accuracy-Performance Tradeoffs on an FPGA through Overclocking

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