Growth of a One Dimensional Quasiperiodic Covering with Locally Determined Decorations

Jeong, Hyeong-Chai

doi:10.3938/jkps.51.1713

Cited by 1 publication

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References 15 publications

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“…As shown in Figure 2b, the capacitance ( C ox ) of the ZrO 2 dielectric can be extracted from the accumulation region, which indicates that the different ALD growth temperature results in the change of C ox . [ 27 ] For the ZrO 2 dielectric grown at 100, 150, 200, 250, and 280 °C, the extracted values of C ox are 0.599, 0.659,0.747, 0.849, and 0.941 μF cm −2 , respectively. It is observed that as the growth temperature increases, the value of the accumulated capacitance increases.…”

Section: Resultsmentioning

confidence: 99%

Multilayer MoS₂ Back‐Gate Transistors with ZrO₂ Dielectric Layer Optimization for Low‐Power Electronics

Zhao

Lin

Cui

et al. 2022

Physica Status Solidi (a)

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Herein, high‐performance back‐gate molybdenum disulfide (MoS2) field‐effect transistors (FETs) with high‐quality sub‐20 nm high‐k dielectric layers are developed for high‐performance and lower‐power consumption applications. The 20 nm ultrathin ZrO2 dielectric layers are deposited by thermal atomic layer deposition (ALD) method, where the growth temperature is varied and it shows a significant impact on the electrical characteristics of the deposited ZrO2 materials. A polydimethylsiloxane (PDMS) transfer process is used to transfer multilayer MoS2 flakes onto a 20 nm ZrO2/p–Si substrate with an optimized dielectric growth temperature without any subsequent processing, resulting in back‐gate MoS2 FET device architecture. These transistors demonstrate excellent electrical characteristics with on–off current ratio up to 1.8 × 107, subthreshold swing as low as 70 mV decade−1 and field‐effect mobility as high as 3.9 cm2 V−1 s−1. Furthermore, an enhancement‐mode device operation and a high complementary metal–oxide–semiconductor (CMOS) ION/IOFF ratio of 107 are achieved. The excellent electrical performance is attributed to the low interface state traps and high‐quality ZrO2 dielectric layer, indicating the great potential of our multilayer MoS2 FETs technology for low‐power applications.

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Section: Resultsmentioning

confidence: 99%

Multilayer MoS₂ Back‐Gate Transistors with ZrO₂ Dielectric Layer Optimization for Low‐Power Electronics

Zhao

Lin

Cui

et al. 2022

Physica Status Solidi (a)

View full text Add to dashboard Cite

show abstract

Growth of a One Dimensional Quasiperiodic Covering with Locally Determined Decorations

Cited by 1 publication

References 15 publications

Multilayer MoS₂ Back‐Gate Transistors with ZrO₂ Dielectric Layer Optimization for Low‐Power Electronics

Multilayer MoS₂ Back‐Gate Transistors with ZrO₂ Dielectric Layer Optimization for Low‐Power Electronics

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Growth of a One Dimensional Quasiperiodic Covering with Locally Determined Decorations

Cited by 1 publication

References 15 publications

Multilayer MoS2 Back‐Gate Transistors with ZrO2 Dielectric Layer Optimization for Low‐Power Electronics

Multilayer MoS2 Back‐Gate Transistors with ZrO2 Dielectric Layer Optimization for Low‐Power Electronics

Contact Info

Product

Resources

About

Multilayer MoS₂ Back‐Gate Transistors with ZrO₂ Dielectric Layer Optimization for Low‐Power Electronics

Multilayer MoS₂ Back‐Gate Transistors with ZrO₂ Dielectric Layer Optimization for Low‐Power Electronics