Hard and soft-breakdown characteristics of ultra-thin HfO/sub 2/ under dynamic and constant voltage stress

Metal-insulator-semiconductor capacitors were fabricated using atomic vapor deposition HfO 2 dielectric with sputtered copper (Cu) and aluminum (Al) gate electrodes. The counterparts with SiO 2 dielectric were also fabricated for comparison. Bias-temperature stress and charge-to-breakdown ( BD ) test were conducted to examine the stability and reliability of these capacitors. In contrast with the high Cu drift rate in an SiO 2 dielectric, Cu in contact with HfO 2 seems to be very stable. The HfO 2 capacitors with a Cu-gate also depict higher capacitance without showing any reliability degradation, compared to the Al-gate counterparts. These results indicate that HfO 2 with its considerably high density of 9.68 g/cm 3 is acting as a good barrier to Cu diffusion, and it thus appears feasible to integrate Cu metal with the post-gate-dielectric ultralarge-scale integration manufacturing processes.

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“…No degradation was observed even though 4-nm-thick HfO was used in Cu-HfO -Si capacitor, as shown in Fig. 3(b) [18].…”

Section: Introductionmentioning

confidence: 85%

<tex>$hbox HfO_2$</tex>MIS Capacitor with Copper Gate Electrode

Perng

Chien

Chen

et al. 2004

IEEE Electron Device Lett.

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“…The proposed devices adopt the symmetrical dual-k spacers made of Hafnium dioxide (HfO 2 ) as a high-k spacer (k = 22) and Silicon dioxide (SiO 2 ) as a low-k spacer (k = 3.9). HfO 2 is known to be highly compatible with silicon process technology when compared to other high-k materials [16]. The effect of varying the high-k spacer length (L HK ) on I on , I off and I on /I off ratio will be investigated for both the n-and p-FinFETs.…”

Section: A Effect Of Inner Hk Spacer Lengthmentioning

confidence: 99%

Low Leakage Current Symmetrical Dual-k 7 nm Trigate Bulk Underlap FinFET for Ultra Low Power Applications

et al. 2019

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The main purpose of this paper is to achieve as low as possible leakage current (I OFF) to meet the requirements for ultra-low power (ULP) applications. The proposed methodology is based on studying the effect of the most effective FinFET design parameters that directly impact its leakage current. The parameters explored in this paper are the effective channel lengths L eff , gate stacks, gate contact materials, and gatesidewall spacers (L sp). The results show that utilizing a symmetrical dual-k material for 7-nm underlap tri-gate FinFETs appreciably allows a sufficient ON current and low leakage current and hence low stand by power consumption. Specifically, the effect of spacer length L sp and L HK is investigated to get low leakage current keeping I ON /I OFF as high as possible. Moreover, the effective channel length in subthreshold conduction (L eff) is maintained greater than the gate length (L g) and the threshold voltage (V th) is adjusted by the proper metal gate work function. The performance of the proposed n-and p-FinFET devices is verified using Sentaurus TCAD simulator from Synopsys. The resulted I OFF is 17 pA/µ m for n-FinFET and 14.7 pA/µm for p-FinFET which are the lowest leakage currents found in recent publications. The achieved I ON /I OFF ratio for both proposed devices is found to be 12.3 × 10 6 and 11 × 10 6 , respectively, which are comparable to the published data. These parameters are obtained for an appropriate choice of L sp = 10 nm and L HK = 5 nm. In addition, the short channel effects variations with L HK have been investigated. INDEX TERMS 7 nm Bulk FinFET, leakage current, SymD-k spacer, TCAD, ultra-low power.

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“…The actual precursor 100 of SBD and of HBD is socalled Progressive Breakdown (PBD), characterized (at least in SiO 2 films thinner than about 2.5 nm) by an increase in the noise level 101 . Figure 12 illustrates these three breakdown modes; they occur in SiO 2 as well as in high-k dielectrics 102,103,105,104 . Interestingly, although PBD and SBD events follow Weibull statistics, their Weibull slopes differ 102,105 , whereby PBD has a smaller slope.…”

Section: Hard Soft and Progressive Breakdownmentioning

confidence: 99%

The Influence of Defects and Impurities on Electrical Properties of High-k Dielectrics

Dąbrowski¹,

Miyazaki

Inumiya

et al. 2008

MSF

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Electrical properties of thin high-k dielectric films are influenced (or even governed) by the presence of macroscopic, microscopic and atomic-size defects. For most applications, a structurally perfect dielectric material with moderate parameters would have sufficiently low leakage and sufficiently long lifetime. But defects open new paths for carrier transport, increasing the currents by orders of magnitude, causing instabilities due to charge trapping, and promoting the formation of defects responsible for electrical breakdown events and for the failure of the film. We discuss how currents flow across the gate stack and how damage is created in the material. We also illustrate the contemporary basic knowledge on hazardous defects (including certain impurities) in high-k dielectrics using the example of a family of materials based on Pr oxides. As an example of the influence of stoichiometry on the electrical pa-rameters of the dielectric, we analyze the effect of nitrogen incorporation into ultrathin Hf silicate films.

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Hard and soft-breakdown characteristics of ultra-thin HfO/sub 2/ under dynamic and constant voltage stress

Cited by 17 publications

References 7 publications

<tex>$hbox HfO_2$</tex>MIS Capacitor with Copper Gate Electrode

<tex>$hbox HfO_2$</tex>MIS Capacitor with Copper Gate Electrode

Low Leakage Current Symmetrical Dual-k 7 nm Trigate Bulk Underlap FinFET for Ultra Low Power Applications

The Influence of Defects and Impurities on Electrical Properties of High-k Dielectrics

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Hard and soft-breakdown characteristics of ultra-thin HfO/sub 2/ under dynamic and constant voltage stress

Cited by 17 publications

References 7 publications

&lt;tex&gt;$hbox HfO_2$&lt;/tex&gt;MIS Capacitor with Copper Gate Electrode

&lt;tex&gt;$hbox HfO_2$&lt;/tex&gt;MIS Capacitor with Copper Gate Electrode

Low Leakage Current Symmetrical Dual-k 7 nm Trigate Bulk Underlap FinFET for Ultra Low Power Applications

The Influence of Defects and Impurities on Electrical Properties of High-k Dielectrics

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Product

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About

<tex>$hbox HfO_2$</tex>MIS Capacitor with Copper Gate Electrode

<tex>$hbox HfO_2$</tex>MIS Capacitor with Copper Gate Electrode