2012
DOI: 10.1109/tcad.2011.2179037
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Hardware Acceleration for Constraint Solving for Random Simulation

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Cited by 3 publications
(1 citation statement)
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“…Constraint-Random Verification: Constraint-random verification offers a highly effective way to deal with the challenges of SoC verification [33,170]. These challenges are overwhelming for many reasons: complex instruction sets, multiple pipeline stages, in-order or out-of-order execution strategies, instruction parallelism, fixedand floating-point scalar/vector operations, and other features that create a seemly never-ending list of corner cases to exercise.…”
Section: Verification Methodsmentioning
confidence: 99%
“…Constraint-Random Verification: Constraint-random verification offers a highly effective way to deal with the challenges of SoC verification [33,170]. These challenges are overwhelming for many reasons: complex instruction sets, multiple pipeline stages, in-order or out-of-order execution strategies, instruction parallelism, fixedand floating-point scalar/vector operations, and other features that create a seemly never-ending list of corner cases to exercise.…”
Section: Verification Methodsmentioning
confidence: 99%