Hardware compilation of application-specific memory-access interconnect

Abstract

Abstract-A major obstacle to successful high-level synthesis (HLS) of large-scale application-specified integrated circuit systems is the presence of memory accesses to a shared-memory subsystem. The latency to access memory is often not statically predictable, which creates problems for scheduling operations dependent on memory reads. More fundamental is that dependences between accesses may not be statically provable (e.g., if the specification language permits pointers), which introduces memory-consistency problems. Addressing these issues with static scheduling results in overly conservative circuits, and thus, most state-of-the-art HLS tools limit memory systems to those that have predictable latencies and limit programmers to specifications that forbid arbitrary memory-reference patterns. A new HLS framework for the synthesis and optimization of memory accesses (SOMA) is presented. SOMA enables specifications to include arbitrary memory references (e.g., pointers) and allows the memory system to incorporate features that might cause the latency of a memory access to vary dynamically. This results in raising the level of abstraction in the input specification, enabling faster design times. SOMA synthesizes a memory access network (MAN) architecture that facilitates dynamic scheduling and ordering of memory accesses. The paper describes a basic MAN construction technique that illustrates how dynamic ordering helps in efficiently maintaining memory consistency and how dynamic scheduling helps alleviate the variable-latency problem. Then, it is shown how static analysis of the access patterns can be used to optimize the MAN. One optimization changes the MAN interconnect topology to increase concurrence. A second optimization reduces the synchronization overhead necessary to maintain memory consistency. Postlayout experiments demonstrate that SOMA's application-specific MAN construction significantly improves power and performance for a range of benchmarks.Index Terms-Communication synthesis, dataflow synthesis, high-level synthesis (HLS), interface design.

Elastic Circuits

“…At the very least, ESL flow is supposed to incorporate a front-end with higher level specifications (e.g., SystemC or ANSI-C) into synthesis flow. There are several interesting publications related to ESL flow for asynchronous (bundled delay) design [44], [114], [115]. This flow is actually closer to a software C-compiler than a hardware synthesis flow.…”

ASTRO: Synthesizing application-specific reconfigurable hardware traces to exploit memory-level parallelism

“…However, while most other studies focus on algorithmic-centric reconfigurable computing architectures, our study focuses primarily on how to exploit memory-level parallelism. Recently, extracting memorylevel parallelism in reconfigurable computing has attracted more attention [28][29][30][31]. For example, recent work [32] proposed a many-cache memory architecture that improves caching in commercially available FPGAs.…”

A New Dataflow Compiler IR for Accelerating Control-Intensive Code in Spatial Hardware

“…Budiu et al identified two primary bottlenecks in their work: significant latency overheads due to a deeply pipelined memory arbitration tree that is necessary to support parallel memory requests [6], as well as performance constraints due to complex control flow [8]. Other projects have attempted to optimize the memory access network for custom hardware by either optimizing for the most frequent accesses [31], partitioning and distributing memory [25], or incorporating cache-like structures [32], [5]. Tartan, a reconfigurable architecture for spatial computation was also developed [33].…”