2015
DOI: 10.1109/tvlsi.2014.2304834
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Hardware Efficient Mixed Radix-25/16/9 FFT for LTE Systems

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Cited by 55 publications
(20 citation statements)
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“…Cases of pipelined FFT processors can be found in [2] and [3]. A pipelined architecture gives high throughputs, however it requires more equipment assets in the meantime.…”
Section: Existing Systemmentioning
confidence: 99%
“…Cases of pipelined FFT processors can be found in [2] and [3]. A pipelined architecture gives high throughputs, however it requires more equipment assets in the meantime.…”
Section: Existing Systemmentioning
confidence: 99%
“…Hundreds of architectures for 128-to 2048-point FFT has been proposed by varying the degree of parallelism and the radix factorization [19] [6]. These implementations are optimized in terms of speed, memory used and hardware logic requirements.…”
Section: Related Workmentioning
confidence: 99%
“…Many FFT implementations have been reported to follow the concept of addressing schemes. Some have used a non-scalable approach targeted to specific applications [8][9][10][11][12]. Others provide scalable implementations in terms the number of FFT points [13][14][15][16][17][18][19][20][21].…”
Section: Introductionmentioning
confidence: 99%