Hardware emulation of Memristor based Ternary Content Addressable Memory

Bahloul, Mohamed A.; Naous, Rawan; Masmoudi, Mohamed

doi:10.1109/ssd.2017.8167029

Cited by 7 publications

(2 citation statements)

References 15 publications

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“…In the case of a Don't care state, the two memristors of a bit‐cell are set to high resistance as shown in Figure 2C. Hence, no path is created to the ground independent of the search bit 54,55 …”

Section: Introductionmentioning

confidence: 99%

Variability analysis of resistive ternary content addressable memories

Bahloul

Fouda

Barraj

et al. 2020

Circuit Theory & Apps

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Resistive ternary content addressable memories (Re-TCAMs) are considered a potential platform for in-memory associative processing. Re-TCAM permits the store and process of the data in the same physical area, allowing inmemory computing. Given the unique properties of the non-volatile memristive device, Re-TCAM is capable of low search energy, large-scale storage, and massively parallel processing. However, like any other semiconductor, memristor as a nanodevice suffers from fabrication process imperfections that provoke a significant variance in their high (R H) and low (R L) resistance states. These variations might lead to the malfunction of the Re-TCAM array and affect its performance and reliability. This paper proposes a simplified mathematical formulation of the memristor state variability for 2T2M bit-cell-based Re-TCAM array. We present a comprehensive statistical design, considering different circuit parameters and variance effects, such as tolerance of memristance variation, the memristor ratio (α = R H =R L), transistor technology, and memory width. The impact of these parameters on the performance is formulated as the probability of error is extensively studied, and a closed-form expression for the optimal threshold voltage is derived. The utility of the presented investigation is illustrated using a design example with real device parameters.

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Section: Introductionmentioning

confidence: 99%

Variability analysis of resistive ternary content addressable memories

Bahloul

Fouda

Barraj

et al. 2020

Circuit Theory & Apps

Self Cite

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“…Another four transistor and two memristor TCAM was proposed where two separate cells were formed with two transistors and one memristor each [24]. All these proposed TCAMs used a memristor as a binary storage cell and two separate memristor bit-cells were used to replace the memory cells of CMOS-based TCAM architecture [25,26]. Reductions in required energy and area were achieved while most of these designs were using separate wiring for each binary cell and thus, complexity in layout.…”

Section: Introductionmentioning

confidence: 99%

Memristor‐transistor hybrid ternary content addressable memory using ternary memristive memory cell

Khan

Rashid

2021

IET Circuits, Devices & Systems

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A memristor-transistor hybrid ternary content addressable memory (MTCAM) with a memristor-based ternary memory cell is proposed. New emerging devices like memristors have recently been explored to overcome the limitations of CMOS-based memory circuits. The memristor is used as a binary memory cell in these MTCAM designs to replace a CMOS-based memory cell. This proposed design used a memristor as a ternary memory cell by exploiting its variable resistance characteristics. The associated wiring is reduced almost by a factor of 2 as a ternary cell is used instead of two binary cells. Area efficiency is further enhanced as the MTCAM cell is comprised of two transistors and two memristors (2T2M). A segmentation technique of match line along with a robust write/ search operation method is presented to enhance the search speed of the proposed MTCAM. Simulation based on a mathematical model of memristor is presented and analysed using 65 nm TSMC MOS model parameters. Corner simulations and Monte Carlo simulations are carried out to substantiate the robustness of the design against process variation. Simulation results show the worst search delay of 0.75 ns and the energy/bit/search of 0.866 fJ for the 128 � 128 bit MTCAM. 1 | INTRODUCTION Large data computation requires massive parallel processing with heavy memory access traffic [1,2]. Content addressable memory (CAM), a widely used hardware search engine for high-speed parallel data search applications [3], provides the capability to search data across an entire memory and returns the address in a single clock cycle [4,5]. Ternary content addressable memory (TCAM) adds more flexibility in the search operation by providing a third state called Mask ('don't care') state. The 'X' state provides a groupsearch option, that is, searching a portion of the word when necessary instead of searching the whole word. This additional 'X' state makes TCAM more powerful in searching by returning match condition regardless of the input search data [6]. TCAM, with its high throughput, is a promising solution for systems that deal with large data, such as a high-speed search engine, data base engine, data mining and multimedia processing [7-9]. CAM density has improved significantly over the past two decades with aggressive CMOS technology scaling [10]. Aggressive scaling of CMOS technology steadily increases the power density of the chip causing a heating problem [11,12]. TCAM needs 2-bit memory to accommodate the third state, 'X'. Multiple (12-16) transistors are thus needed to form TCAM cells, which require large area and, eventually, high power consumption [4]. This area and power constraint limits the usage of CMOS-based TCAM in network and classification applications [13,14]. New emerging devices such as magnetotunnelling junction-based devices [15], metamaterials-based optical nano circuits [16], carbon nanotube field effect transistors [17] and memristors [18,19] are being explored to find solutions for these area and power limitations of their CMOS counterpart. Memristor, among...

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