Hardware-optimal test register insertion

Stroele, A.P.; Wunderlich, Hans-Joachim

doi:10.1109/43.703833

Cited by 27 publications

(12 citation statements)

References 35 publications

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“…4 as a conventional technique and the proposed method (single-control testable design for testability method) will be compared for the hardware overhead after design for testability and the fault detection rate. The RTL benchmark circuits used in the experiments are GCD and Paulin [9], 3rd Lattice Wave Filter (LWF), and 4th IIR.…”

Section: Resultsmentioning

confidence: 99%

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A DFT method for BIST of RTL data paths based on single‐control testability

Izutsu¹,

Wada²,

Masuzawa³

et al. 2003

Electron Comm Jpn Pt II

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SUMMARYIn this paper, as a built-in self-test (BIST) scheme for register transfer level data paths, we will propose a BIST of the test per clock scheme based on hierarchical testing. In this technique, test pattern generators and response analyzers are added only to primary inputs and primary outputs of circuit under test; and for the respective combinational circuit elements, the test patterns and corresponding responses are propagated by using paths on a data path. In this paper, as a data path capable of BIST based on this hierarchical testing, we will define a single-control testable data path, and propose a design for testability method for changing the design from a given data path to a single-control testable data path. Moreover, the evaluation of the proposed technique is performed using benchmark circuits.

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Section: Resultsmentioning

confidence: 99%

“…4 has reported a design for testability method in which the design is changed in such a way that all closed circuits inside the circuit contain two BILBOs or one CBILBO.…”

Section: Introductionmentioning

confidence: 99%

A DFT method for BIST of RTL data paths based on single‐control testability

Izutsu¹,

Wada²,

Masuzawa³

et al. 2003

Electron Comm Jpn Pt II

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show abstract

“…At the gate level, the module under test is subjected to error simulations to evaluate error detection rates. The SC and CSC methods have high error-detection rates, and compared to the method proposed by Stoele and Wunderlich [2], have low hardware overhead. Under the SC method, the test is combined with each module individually, which results in long testing times; the CSC method can be combined with multiple modules simultaneously.…”

Section: Introductionmentioning

confidence: 97%

“…Test-per-clock has short test-execution times, and can be used for delayed errors, which must extend a test pattern over consecutive cycles. Stoele and Wunderlich [2] proposed Design for Testability (DFT), specifically BILBO [3], which requires at least two closed circuits to be present, and CBILBO [4], which requires one. The problem with this approach is high hardware overhead.…”

Section: Introductionmentioning

confidence: 99%

Hierarchical BIST: Test‐per‐clock BIST with low overhead

Yamaguchi

Inoue

Fujiwara

2007

Electron Comm Jpn Pt II

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SUMMARYWe have proposed a hierarchical built-in self-test (BIST) mechanism for register-transfer level (RTL) circuits, to simplify testing design methods. Hierarchical BIST is a two-layered approach to BIST that operates at the register-transfer level and gate level. At the register-transfer level, the test-pattern generator creates a test pattern and applies it to the module under test, and creates a pathway that enables the response analyzer to monitor the results. At the gate level, the error-detection rate for the module under test is tested by simulating errors. An advantage of the hierarchical BIST approach is that high detection rates can be achieved with low hardware overhead. In this paper, we propose time-division single-control testability as a testability model for hierarchical BIST. We conducted tests that demonstrate this is an effective way to reduce test execution time and hardware overhead.

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“…Paper [2] even gives an algorithm to compute the optimum solutions for breaking loops. Later on, breaking loops method was also adapted to BIST [3].…”

Section: Introductionmentioning

confidence: 99%

Fast computation of data correlation using BDDs

Zeng

Zhang

Harris

et al.

2003 Design, Automation and Test in Europe Conference and Exhibition

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Data correlation is a well-known problem that causes difficulty in VLSI testing. Based on a correlation metric, an efficient heuristic to select BIST registers has been proposed in the previous work. However, the computation of data correlation itself was a computational intensive process and became a bottleneck in the previous work. This paper presents an efficient technique to compute data correlation using Binary Decision Diagrams (BDDs). Once a BDD is built, our algorithms take linear time to compute the corresponding data correlation. The experimental results show that this technique is much faster than the previous technique based on simulation. It enables testing approaches based on data correlation to handle more practical designs. As one of the successful applications, partial scan is demonstrated by integrating our computation results.

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Hardware-optimal test register insertion

Cited by 27 publications

References 35 publications

A DFT method for BIST of RTL data paths based on single‐control testability

A DFT method for BIST of RTL data paths based on single‐control testability

Hierarchical BIST: Test‐per‐clock BIST with low overhead

Fast computation of data correlation using BDDs

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