2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) 2017
DOI: 10.1109/isvlsi.2017.69
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Hardware Security for Critical Infrastructures - The CIPSEC Project Approach

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Cited by 6 publications
(4 citation statements)
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“…We present hereby the PLS-Box with a high-level description of its functionalities. The PLS-Box is conceptually similar to hardware-security-module (HSM) [81] or Trusted-Platform-Module [82,83]. The goal of the PLS-Box is to perform CRKG from the received communication data, as depicted by the block diagram in Fig.…”
Section: Pls Boxmentioning
confidence: 99%
“…We present hereby the PLS-Box with a high-level description of its functionalities. The PLS-Box is conceptually similar to hardware-security-module (HSM) [81] or Trusted-Platform-Module [82,83]. The goal of the PLS-Box is to perform CRKG from the received communication data, as depicted by the block diagram in Fig.…”
Section: Pls Boxmentioning
confidence: 99%
“…Security Monitoring loggers installed on such devices need to rely on an execution environment that is capable of supporting the ADS sensors' functionality and that is protected from malicious entities. To achieve high security in legacy devices, it has been proposed in several works to introduce external security tokens that can be considered trusted [23,[28][29][30]. Having that in mind, extending the work in [2], we propose a Hardware Security Token (HST) that could be used as an external security element on legacy devices in order to instill a level of trust on collected ADS sensor logs and provide a series of security services to an associated host device and user.…”
Section: Proposed Approach For Legacy Systemsmentioning
confidence: 99%
“…The HST is a synchronous System on Chip (SoC) device based on an ARM microprocessor with TrustZone support (e.g., ARM Cortex A processor class) that is connected through an AMBA AXI bus to a series of cryptographic accelerator peripheral IP cores and storage elements like RAM, ROM, and NVRAM memory modules. The cryptography accelerator peripherals act as a security element of the ARM Trustzone enabled processor and consist of an RSA signature unit, an Elliptic Curve (EC) Point Operation unit (ECPO), a SHA256 hash function unit as well as a symmetric key encryption/decryption and key generation unit (using the AES algorithm), following an architecture similar to the one presented in [29]. All the HST IP cores are protected against semi-invasive and non invasive attacks [23,31,32].…”
Section: Hst Architecturementioning
confidence: 99%
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