Hardware sorter and its application to data base machine

Dohi, Y.; Suzuki, Akira; Matsui, Noriyuki

doi:10.1145/1067649.801730

Cited by 9 publications

(2 citation statements)

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“…A high-capacity cellular array that sorts by enumeration is investigated by Yasuura et al [1982]. In Dohi et al [1982], cells that are able to sort-merge data in compressed form are connected in a binary tree topology to constitute a powerful sorter. In both cases, the design of the basic cell is simple enough to allow very high density packaging with current or near-future technology.…”

Section: Summary and Recent Resultsmentioning

confidence: 99%

“…By implementing the sequence of comparison and move steps required by an efficient sorting algorithm in hardware, one could realize a low-cost, fast, hardware device that would significantly lighten the burden on the CPU. Several alternative designs of hardware sorters recently have been proposed [Chen et al 1978;Chung et al 1980;Dohi et al 1982;Lee et al 1981;Thompson 1983;Yasuura et al 1982], and preliminary evaluations seem to indicate that a VLSI implementation of sorting devices could soon become feasible. The relatively simple logic required for sorting constitutes a strong argument in favor of this approach.…”

Section: Hardware Sortersmentioning

confidence: 99%

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A taxonomy of parallel sorting

et al. 1984

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We propose a taxonomy of parallel sorting that encompasses a broad range of array-and file-sorting algorithms. We analyze how research on parallel sorting has evolved, from the earliest sorting networks to shared memory algorithms and VLSI sorters.In the context of sorting networks, we describe two fundamental parallel merging schemes: the odd-even and the bitonic merge. We discuss sorting algorithms that evolved from these merging schemes for parallel computers, whose processors communicate through interconnection networks such as the perfect shuffle, the mesh, and a number of other sparse networks. Following our discussion of network sorting algorithms, we describe how faster algorithms have been derived from parallel enumeration sorting schemes, where, with a shared memory model of parallel computation, keys are first ranked and then rearranged according to their rank.Parallel sorting algorithms are evaluated according to several criteria related to both the time complexity of an algorithm and its feasibility from the viewpoint of computer architecture. We show that, in addition to attractive communication schemes, network sorting algorithms have nonadaptive schedules that make them suitable for implementation. In particular, they are easily generalized to block sorting algorithms, which utilize limited parallelism to solve large sorting problems. We also address the problem of sorting large mass-storage files in parallel, using modified disk devices or intelligent bubble memory. We conclude by mentioning VLSI sorting as an active and promising direction for research on parallel sorting.

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Section: Summary and Recent Resultsmentioning

confidence: 99%

Section: Hardware Sortersmentioning

confidence: 99%