Harmonic minimization of a single-phase asymmetrical TCHB multilevel inverter based on nearest level control method

Saleh, Wail Ali Ali; Said, Nurul Ain Mohd; Halim, Wahidah Abd

doi:10.11591/ijpeds.v11.i3.pp1406-1414

Cited by 10 publications

(3 citation statements)

References 28 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Level shifted PWM implemented on cascaded H-bridge topology has been discussed in detail in [24]. Low-frequency techniques offer the advantages of low switching loss as the number of switching in a particular cycle is less [25]. Nearest level control (NLC) is a fundamental frequency switching technique which is used in the proposed MLI to obtain the switching signals.…”

Section: Modulation Strategymentioning

confidence: 99%

Modified asymmetrical 13-level inverter topology with reduce power semiconductor devices

Arif

Sarwer

Ayob

et al. 2020

IJPEDS

View full text Add to dashboard Cite

This paper introduces a modified multilevel inverter topology with asymmetrical dc sources combination. The significant features of the proposed circuit are the reduced number of switches and low total standing voltage (TSV). Proposed topology utilizes ten switches to produce 13 level output with per unit TSVp.u of 5.33. An additional feature of the proposed topology is the inherent negative level generation as there is no requirement of an H-bridge for the polarity reversals. Nearest level control (NLC) technique is used as the modulation strategy. Performance of the proposed topology is validated through extensive analysis using Simulink and PLECS software. Detailed circuit analysis and its power loss, as well as efficiency studies, have been carried out under constant and dynamic load conditions. Results obtained shows that the proposed topology is working well, producing an output of 13-level with total harmonic distortion of 6.36% and inverter efficiency of 98.8%. The topology is extended to n-level structure, and its generalized expressions for different parameters were formulated. The comparison of the generalized structure with other existing topology is carried out, and it is found that the proposed topology outperform other topologies on many parameters.

show abstract

Section: Modulation Strategymentioning

confidence: 99%

Modified asymmetrical 13-level inverter topology with reduce power semiconductor devices

Arif

Sarwer

Ayob

et al. 2020

IJPEDS

View full text Add to dashboard Cite

show abstract

“…It is easy to build and control. The problem of the cascaded MLI is needing single-separated DC voltage source, which may be not balanced at all phases of inverter [2]. The Cascaded MLI is good for renewable energy applications such as PV energy system as a separate-DC-sources [3].…”

Section: Introductionmentioning

confidence: 99%

Design and implementation of reduced number of switches for new multilevel inverter topology without zero-level state

Antar

Hussein

Abdullah

2022

IJPEDS

View full text Add to dashboard Cite

<p>Currently, multilevel inverter (MLI) has been chosen over conventional inverter because of less harmonic distortions and higher output voltage levels. In this paper, 15 level inverter with reduced number of power switching devices is designed. Different output voltage levels can be obtained including zero level or with none zero level (NoneZero level). Single phase MLI inverter with 7 switches is built, simulated, and implemented practically. The system depending on modified absolute sinusoidal pulse width modulation (MASPWM) controller strategy is adopted. Simulation results clarified that MLI with NoneZero level provides output voltage with total harmonic distortion (THD) percent less than with zero level. The THD of the 15 level output voltage with zero level is 3.39%, while with NoneZero level is 3%, respectively. The system is tested at different output levels. The THD values at different output voltage levels is reduced by 12% depending on NoneZero level state. Depending on what has been achieved, the system has been implemented practically with NoneZero<br />level and the THD value was 3.1%. These results prove the success of the suggested MLI circuit and MASPWM controller to obtain the required voltage level and THD.</p>

show abstract

“…The Symmetrical arrangement exists when the DC voltage sources of the TCHB cells have equal values, whereas the asymmetrical arrangement exists when the DC input voltage values are different. Symmetrical and asymmetrical arrangements of TCHB inverter can be found in [8][9][10][11].…”

Section: Introductionmentioning

confidence: 99%

Voltage harmonics reduction in single phase 9-level transistor clamped H-bridge inverter using nearest level control method

Said

Saleh

Halim

2020

IJEECS

Self Cite

View full text Add to dashboard Cite

This paper proposes a nearest level control method based modulation scheme for a 9-level symmetrical Transistor Clamped H-bridge (TCHB) inverter. The topology has gained increasing research focus due to its advantages in obtaining high quality output while using a reduced number of electronic components. The device count for obtaining a 9-level output voltage is it uses 10 active switches as compared to the 16 being used in a conventional 9-level cascaded H-Bridge (CHB) inverter. The significant contribution of the research is the development of the NLC modulation technique that operates at the fundamental frequency, thus reducing switching losses, and able to reduce harmonic content significantly. The reduced harmonic content can lessen the power quality problem. The NLC modulation scheme, shows that the overall THD is reduced without the need for filtration. The 50 values of harmonic content will be count that follows the IEEE Standard 519. MATLAB/Simulink based simulations and experimental results obtained from the laboratory prototype of a single-phase TCHB inverter feeding a R load validate the theoretical analyses and effectiveness of the proposed modulation scheme.

show abstract

Harmonic minimization of a single-phase asymmetrical TCHB multilevel inverter based on nearest level control method

Cited by 10 publications

References 28 publications

Modified asymmetrical 13-level inverter topology with reduce power semiconductor devices

Modified asymmetrical 13-level inverter topology with reduce power semiconductor devices

Design and implementation of reduced number of switches for new multilevel inverter topology without zero-level state

Voltage harmonics reduction in single phase 9-level transistor clamped H-bridge inverter using nearest level control method

Contact Info

Product

Resources

About