HArtes: Hardware-Software Codesign for Heterogeneous Multicore Platforms

Bertels, Koen; Sima, Vlad-Mihai; Yankova, Y.; Kuzmanov, Georgi; Luk, Wayne; Coutinho, G; Ferrandi, Fabrizio; Pilato, Christian; Lattuada, Marco; Sciuto, D.; Michelotti, Andrea

doi:10.1109/mm.2010.91

Cited by 24 publications

(18 citation statements)

References 8 publications

(5 reference statements)

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“…The task management costs have been obtained by applying the profiling technique proposed in [17]. Mapping decisions for these architectures have been obtained by applying the methodology proposed in [4] and then specified as source code annotations [39]. This approach automatically produces a partitioning of the resources among parallel tasks at each level of the hierarchy.…”

Section: Methodsmentioning

confidence: 99%

“…Similarly to [38] and [39], we adopt the Hierarchical Task Graph (HTG) as the intermediate representation of a partitioned application. Specifically, the HTG is an acyclic directed graph whose vertices can be: simple (i.e.…”

Section: Definitionsmentioning

confidence: 99%

“…Finally, mapping decisions are specified through custom code annotations, as in [39], and the information is associated with each task of graph.…”

Section: Definitionsmentioning

confidence: 99%

“…This work targets embedded systems composed of a set of processors, which feature local memories for instructions and data [5,39], and no operating system, but with a bare-metal synchronization, as in [39,40]. We currently support ARM processors (with or without support for out-of-order execution) and DSPs.…”

Section: Supported Target Architecturesmentioning

confidence: 99%

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Performance Estimation of Task Graphs Based on Path Profiling

Lattuada

Pilato

Ferrandi

2015

Int J Parallel Prog

Self Cite

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Correctly estimating the speed-up of a parallel embedded application is crucial to efficiently compare different parallelization techniques, task graph transformations or mapping and scheduling solutions. Unfortunately, especially in case of control-dominated applications, task correlations may heavily affect the execution time of the solutions and usually this is not properly taken into account during performance analysis. We propose a methodology that combines a single profiling of the initial sequential specification with different decisions in terms of partitioning, mapping, and scheduling in order to better estimate the actual speed-up of these solutions. We validated our approach on a multi-processor simulation platform: experimental results show that our methodology, effectively identifying the correlations among tasks, significantly outperforms existing approaches for speed-up estimation. Indeed, we obtained an absolute error less then 5% in average, even when compiling the code with different optimization levels.

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Section: Methodsmentioning

confidence: 99%

Section: Definitionsmentioning

confidence: 99%

“…Finally, mapping decisions are specified through custom code annotations, as in [39], and the information is associated with each task of graph.…”

Section: Definitionsmentioning

confidence: 99%

Section: Supported Target Architecturesmentioning

confidence: 99%

See 2 more Smart Citations

Performance Estimation of Task Graphs Based on Path Profiling

Lattuada

Pilato

Ferrandi

2015

Int J Parallel Prog

Self Cite

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“…Bertels et al present HArtes [11], a fully or semi-automatic tool implemented under GCC. The toolchain is capable of extracting functional parallelism inside the target code and issues OpenMP-based executables with mapping directives, which are executed by a specific runtime system.…”

Section: Related Workmentioning

confidence: 99%

Turning control flow graphs into function calls: Code generation for heterogeneous architectures

Barrio

Carreras

Sierra

et al. 2012

2012 International Conference on High Performance Computing &Amp; Simulation (HPCS)

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Heterogeneous machines are gaining momentum in the High Performance Computing field, due to the theoretical speedups and power consumption. In practice, while some applications meet the performance expectations, heterogeneous architectures still require a tremendous effort from the application developers. This work presents a code generation method to port codes into heterogeneous platforms, based on transformations of the control flow into function calls. The results show that the cost of the function-call mechanism is affordable for the tested HPC kernels. The complete toolchain, based on the LLVM compiler infrastructure, is fully automated once the sequential specification is provided.

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Introduction

Cardoso

Hübner

2011

Reconfigurable Computing

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HArtes: Hardware-Software Codesign for Heterogeneous Multicore Platforms

Cited by 24 publications

References 8 publications

Performance Estimation of Task Graphs Based on Path Profiling

Performance Estimation of Task Graphs Based on Path Profiling

Turning control flow graphs into function calls: Code generation for heterogeneous architectures

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