Heat-removal performance scaling of interlayer cooled chip stacks

Abstract

Interlayer cooling is the only heat removal concept which scales with the number of active tiers in a vertically integrated chip stack. In this work, we numerically and experimentally characterize the performance of a three tier chip stack with a footprint of 1cm2. The implementation of 100m pitch area array interconnect compatible heat transfer structures results in a maximal junction temperature increase of 54.7K at 1bar pressure drop with water as coolant for 250W/cm2 hot-spot and 50W/cm2 background heat flux. The total power removed was 390W which corresponds to a 3.9kW/cm 3 volumetric heat flow. An efficient multi-scale modeling approach is proposed to predict the temperature response in the complete chip stack. The experimental validation confirmed an accuracy of +/- 10%. Detailed sub-domain modeling with parameter extraction is the base for the system level porous-media calculations with thermal field-coupling between solid - fluid and solid - solid interfaces. F urthermore, the strength and weakness of microchannel and pin fin heat transfer geometries in 2-port and 4-port fluid architectures is identified. Microchannels efficiently mitigate hot spots by distributing the dissipated heat to multiple cavities due to their low porosity. Pin fins with improved permeability and convective heat dissipation are advantageous at small power map contrast and aligned hot spots on the different tiers. Large stacks of 4cm2 can be cooled sufficiently by the 4-port fluid delivery architecture. The flow rate is improved four times compared to the 2-port fluid manifold. The non-uniformity of the flow in case of the 4-port demands a more careful floor-planning. Furthermore optimization schemes such as hot-spot distribution, individual hot-spot heat flux adjustment, as well as hot-spot sub-millimeter dimensioning to minimize pumping power and maximize chip stack performance are proposed

A semi-analytical approach for optimized design of microchannel liquid-cooled ICs

“…In such scenarios where there are few local minima in the design space, gradient descent algorithms such as non-linear pro- are shown in Table I [2,4]. It is important to note that our used maximum channel width (w Cmax = 50µm) is the most common channel width used in previous works [3][4][5].…”

“…In this experiment, we apply the proposed method to different liquid-cooled 3D-MPSoC architectures to demonstrate (b) Non-uniform heat flux Cmax common channel width used in previous works [3][4][5].…”

“…While in Test B, Fig. 4(b), the top and the bottom silicon dies are divided into a group of segments, such that in each segment, a random heat flux value in the interval [50, 250] W/cm 2 is applied, which is the range of power densities typically used to model the non-uniform heat dissipation of ICs in the literature [3]. Although Test B thermal gradient by 32% (19 o C in Test A and 48 o C in T B) even for these high-heat flux scenarios.…”

“…1. Significant progress has been made in the development and validation of such advanced thermal packages [3,4].…”

Floorplanner for multi-core micro-processors in 3D ICs with interlayer cooling system

“…Interlayer cooling can remove the internal heat flux of processor effectively, and is the only feasible heat removal solution for multiple active layers in 3D ICs so far [8,9]. In this scheme, the coolant pass through the fluid cavities between the active layers, and remove the internal heat flux as Fig.…”