Heavy ion-induced digital single-event transients in deep submicron Processes

Benedetto, J.M.; Eaton, P.H.; Avery, Keith; Mavis, D.G.; Gadlage, Matthew J.; Turflinger, T.L.; Dodd, P.E.; Vizkelethyd, G.

doi:10.1109/tns.2004.839173

Cited by 112 publications

(35 citation statements)

References 18 publications

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“…As expected, this also confirms that larger LETs result in larger pulse widths. It is interesting to note that the SET pulse widths predicted from these simulations are relatively smaller than observed for earlier technology nodes in [1][7] [9]. Although a direct comparison with transient current measurements reported in [8] cannot be made because of very large size devices under test and a different technology used in that work (50nm), our simulations agree with the trend that SET pulse widths are getting smaller in sub-100nm technologies.…”

Section: Set Pulse Widths For Large Letssupporting

confidence: 77%

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Critical charge and set pulse widths for combinational logic in commercial 90nm cmos technology

Naseer

Draper

Boulghassoul

et al. 2007

Proceedings of the 17th ACM Great Lakes Symposium on VLSI

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This work presents an efficient hybrid simulation approach, developed for accurate characterization of single-event transients (SETs) in combinational logic. Using this approach, we show that charges as small as 3.5fC can introduce transients in commercial 90nm CMOS technology, hence increasing the likelihood of SETinduced soft errors. SET pulse-widths as large as 942ps are predicted at an LET (Linear Energy Transfer) of 60MeV-cm 2 /mg. Process-corner variations are shown to modulate SET pulse-widths by up-to 75%. The results suggest that selection of mitigation techniques for SET radiation-hardened circuits cannot exclusively rely on baseline process analyses, as they might grossly underestimate the true SET risk to the design.

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Section: Set Pulse Widths For Large Letssupporting

confidence: 77%

“…Numerous efforts have been made to indirectly characterize SETs through experimentation [1][7] [9]. A more recent effort by FerletCavrois et al [8] succeeded in measuring transient current pulses on relatively large devices in real-time conditions.…”

Section: Introductionmentioning

confidence: 99%

Critical charge and set pulse widths for combinational logic in commercial 90nm cmos technology

Naseer

Draper

Boulghassoul

et al. 2007

Proceedings of the 17th ACM Great Lakes Symposium on VLSI

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show abstract

“…This can be easily explained by the lower charge requirements to represent a logic HIGH state (resulting in higher number of SETs) and the increased number of clock edges for latching SETs [3]. Recent work suggests that for 0.25 µm and smaller technologies, SETs in combinational logic will dominate single-event related reliability issues [6]. As a result, it is important to understand the SET characteristics and their effects on overall circuit operation.…”

Section: Introductionmentioning

confidence: 99%

On-Chip Characterization of Single-Event Transient Pulsewidths

Narasimham

Ramachandran

Bhuva

et al. 2006

IEEE Trans. Device Mater. Relib.

132

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Abstract-A new on-chip Single Event Transient (SET) test structure has been developed that can autonomously measure the width of random SET pulses. Simulation results show measurement granularity of 900 ps for a 1.5 µm technology and 65 ps for 0.13 µm technology. Laser tests were used to obtain experimental data on test chips fabricated using 1.5 µm process. Experimental measurements show pulse widths varying from 900 ps to over 3 ns as the laser energy is increased.Index Terms-Single event transient (SET), transient pulse width

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“…This combats the interlocking feedback paths from fighting latch input signals. All four storage nodes can be written at once to improve write speed [24]. Implementing DICE latches in layout provides a compact, low power design.…”

Section: ) Dual Interlock Storage Cellsmentioning

confidence: 99%

Redundancy Based on a Fault-Tolerant Gate Array Cell

Tyurin¹,

Kamenskih²

2017

VVSUTR

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Radiation hardening by design (RHBD) has become a necessary practice when creating circuits to operate within radiated environments. While employing RHBD techniques has tradeoffs between size, speed and power, novel designs help to minimize these penalties. Space radiation is the primary source of radiation errors in circuits and two types of single event effects, single event upsets (SEU), and single event transients (SET) are increasingly becoming a concern. While numerous methods currently exist to nullify SEUs and SETs,

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Heavy ion-induced digital single-event transients in deep submicron Processes

Cited by 112 publications

References 18 publications

Critical charge and set pulse widths for combinational logic in commercial 90nm cmos technology

Critical charge and set pulse widths for combinational logic in commercial 90nm cmos technology

On-Chip Characterization of Single-Event Transient Pulsewidths

Redundancy Based on a Fault-Tolerant Gate Array Cell

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