Helper threads via virtual multithreading on an experimental itanium
            <sup>®</sup>
            2 processor-based platform

Wang, Perry H.; Collins, Jamison D.; Wang, Hong; Kim, Dong-Keun; Greene, Bill; Chan, Kai-Ming; Yunus, Aamir B.; Sych, Terry; Moore, Stephen F.; Shen, John Paul

doi:10.1145/1037187.1024411

Cited by 5 publications

(3 citation statements)

References 23 publications

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“…Helper threads [28,14,7,31,16] have been used to speculatively execute a code region to reduce the latency of its expensive instructions. In these research efforts, a helper thread typically serves the purposes of data prefetching or branch predictions or both.…”

Section: Related Workmentioning

confidence: 99%

Exploiting Speculative TLP in Recursive Programs by Dynamic Thread Prediction

Gao

Lian

Xue

et al. 2009

Lecture Notes in Computer Science

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Abstract. Speculative parallelisation represents a promising solution to speed up sequential programs that are hard to parallelise otherwise. Prior research has focused mainly on parallelising loops. Recursive procedures, which are also frequently used in real-world applications, have attracted much less attention. Moreover, the parallel threads in prior work are statically predicted and spawned. In this paper, we introduce a new compiler technique, called Speculative Parallelisation of Recursive Procedures (SPRP), to exploit speculative TLP (thread-level parallelism) in recursive procedures. SPRP combines a dynamic thread-spawning policy and a live-in prediction mechanism in a single helper thread that executes a distilled version of a procedure on a dedicated core. It serves to predict both the invocation order of recursive calls and their live-ins in concert and dispatches these calls to the other cores in a multicore system for parallel execution. To our knowledge, SPRP is the first compiler technique to speculatively parallelise recursive procedures this way. Compared with existing static thread prediction techniques, dynamic thread prediction reduces the number of useless threads spawned, and consequently, misspeculation overhead incurred. Our preliminary results demonstrate that this technique can speedup certain recursive benchmarks that are difficult to parallelise otherwise.

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Section: Related Workmentioning

confidence: 99%

Exploiting Speculative TLP in Recursive Programs by Dynamic Thread Prediction

Gao

Lian

Xue

et al. 2009

Lecture Notes in Computer Science

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“…On a follow-up paper [6], Kim and Smith discuss the microarchitecture and ISA that implements this distributed processing paradigm, which utilizes hierarchical register files and a global register file to hold global state. Wang et al introduce virtual multithreading to run helper threads on processors that do not have built-in hardware support for multitreading [22]. In Section 4, we detail the prior work for each individual helper when discussing the implementation of that helper.…”

Section: Related Workmentioning

confidence: 99%

Improving the performance and power efficiency of shared helpers in CMPs

Shayesteh

Reinman

Jouppi

et al. 2006

Proceedings of the 2006 International Conference on Compilers, Architecture and Synthesis for Embedded Systems

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Technology scaling trends have forced designers to consider alternatives to deeply pipelining aggressive cores with large amounts of performance accelerating hardware. One alternative is a small, simple core that can be augmented with latency tolerant helpers. As the demands placed on the processor core varies between applications, and even between phases of an application, the benefit seen from any set of helpers will vary tremendously. If there is a single core, these auxiliary structures can be turned on and off dynamically to tune the energy/performance of the machine to the needs of the running application.As more of the processor is broken down into helpers, and additional cores are added to a single chip that can potentially share helpers, the decisions that are made about these structures become increasingly important. In this paper we describe the need for methods that effectively manage these helpers. Our counter-based approach can dynamically turn off three helpers on average while staying within 2% of the performance when running with all helpers. In a multicore environment, our intelligent and flexible sharing of helper provides an average 24% speedup compared to static sharing in conjoined cores. Furthermore we show a benefit from constructively sharing helpers among multiple cores running the same application.

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“…Recent years have seen many proposed [3,4,6,7,15,17,18,21,24,25] and even some prototype [23] implementations of pre-execution. These have targeted both loads and branches and have used both software and hardware to generate and spawn p-threads.…”

Section: Related Workmentioning

confidence: 99%