HERMES: an infrastructure for low area overhead packet-switching networks on chip

Moraes, Fernando; Calazans, Ney; Mello, Ana Maria Lisboa de; Möller, Leandro; Ost, Luciano

doi:10.1016/j.vlsi.2004.03.003

Cited by 425 publications

(274 citation statements)

References 31 publications

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“…C-NoC groups nodes, based on their communication density, and connect these nodes to the same router. To do this, they proposed a modified router architecture, based on Hermes NoC [11]. The modified router partitions the system to local and remote ports.…”

Section: Related Workmentioning

confidence: 99%

Networks-on-Chip Interfacing: NoC-based Systems Networking and Inter-NoC Communication

Hassan¹

2017

IJCDS

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Many-and multi-core Networks-on-Chip (NoC) systems have a large spectrum of applications, and one of these applications is High Performance Computing (HPC). In HPC application, system scalability is one of the important features of a given HPC platform. Two of the factors governing scalability are the interfacing link speed and the ease of deploying additional processing nodes. For NoC-based systems, scalability has two meanings; intra-NoC scalability, which includes partitioning and clustering Processing Elements (PEs) to achieve better performance, and inter-NoC scalability, which includes interfacing with other NoC-based systems via inter-NoC links and creating a newtrok of multiple NoC-based systems. In this paper, we investigate the case of inter-NoC communication between a network of NoC-based systems. By using our simulator, we found out that treating a network of NoC-based systems as a generic case of interfacing yields non-optimal performance. To target the inter-NoC communication performance, we introduce NoC 2 , an NoC-based system with an Ethernet communication manager that provides better management for inter-NoC traffic. Current implementations of inter-NoC traffic management handle inter-NoC traffic using software running on top of a dedicated PE, whereas NoC 2 is designed so that the software running on cores within the NoC is completely abstracted from inter-NoC traffic management. Experiments show that this kind of abstraction has better inter-NoC communication performance over generic NoC interfaced via Ethernet. Results suggest that NoC 2 would perform better when it comes to scaling NoC-based systems by interfacing more NoC-based hardware.

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Section: Related Workmentioning

confidence: 99%

Networks-on-Chip Interfacing: NoC-based Systems Networking and Inter-NoC Communication

Hassan¹

2017

IJCDS

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“…One of the main challenges in today's hardware architectures resides in implementing versatile communication capabilities that are able to provide a sufficient bandwidth whilst remaining cost-and size-efficient, as evidenced in research on Network-On-Chip [2] and other systems [8]. This aspect of parallel systems is unfortunately often ignored in bio-inspired hardware approaches and is another of the factors that prevent the implementation of complex applications.…”

Section: The Communication Infrastructurementioning

confidence: 99%

“…To route the data between the different Mercury interfaces, we used the switch-box element of the Hermes framework [8] in a slightly modified version to handle serial data transmissions. Its role is to redirect packets, using the addresses embedded in the data headers, that could come from any direction to any other direction, enabling point-to-point communication between any arbitrary pair of Cell boards in the whole Confetti system.…”

Section: Transport Layer -The Mercury Interfacementioning

confidence: 99%

A Hardware-Software Design Framework for Distributed Cellular Computing

Mudry

Ruffin

Ganguin

et al. 2008

Evolvable Systems: From Biology to Hardware

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Abstract. In this article, we describe a novel hardware-software design framework for prototyping cellular architectures in hardware. Based on an extensible platform of about 200 FPGAs, configured as a networked structure of processors, the hardware part of this computing framework is backed by an extensible library of software components that provides primitives for efficient inter-processor communication and distributed computation. This dual software-hardware approach allows a very quick exploration of different ways to solve computational problems using bio-inspired techniques. To demonstrate the validity of the method, we present an example of how a traditional parallel system such as a cellular automaton can be modeled and run with this perspective. In addition, we also show that the flexibility of our approach allows not only cellular automata but any computation to be easily implemented on a cellular substrate.

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“…Our scheduler is different from the schedulers in ASIC-targeted NoC routers, since our network topology is reconfigurable on demand and our scheduler utilizes the reconfigurability. NoCs targeting FPGAs (for example, [5][6] [7]) employ fixed topologies defined at design-time. The topology is defined by the interconnections between routers and the crossbar inside the router also accommodates internally all-to-all physical interconnects.…”

Section: Related Workmentioning

confidence: 99%