Abstract:A chip-level hermetic package for a high-temperature graphene pressure sensor was investigated. The silicon cap, chip and substrate were stacked by Cu–Sn and Au–Au bonding to enable wide-range measurements while guaranteeing a high hermetic package. Prior to bonding, the sample was treated with Ar (5% H2) plasma. The Cu–Sn bonding was firstly performed at 260 °C for 15 min with a pressure of 9.9 MPa, and the corresponding process conditions for Au–Au bonding has increased to 300 °C, 20 min and 19.8 MPa respect… Show more
“…To reduce the wettability of the glass paste on the Au electrode, they grow a silicon dioxide isolation layer on the surface of golden lead via chemical vapor deposition. Wang et al investigate the chip-level hermetic package for a high-temperature graphene pressure sensor and demonstrate that the combination of Cu–Sn and Au–Au is extremely suitable for hermetic packaging [ 4 ]. Wu et al provide theoretical support for the application of thin coatings at high temperatures and in harsh environments [ 5 ].…”
Unlike transistors, the continuous downscaling of feature size in CMOS technology leads to a dramatic rise in interconnect resistivity and concomitant performance degradation [...]
“…To reduce the wettability of the glass paste on the Au electrode, they grow a silicon dioxide isolation layer on the surface of golden lead via chemical vapor deposition. Wang et al investigate the chip-level hermetic package for a high-temperature graphene pressure sensor and demonstrate that the combination of Cu–Sn and Au–Au is extremely suitable for hermetic packaging [ 4 ]. Wu et al provide theoretical support for the application of thin coatings at high temperatures and in harsh environments [ 5 ].…”
Unlike transistors, the continuous downscaling of feature size in CMOS technology leads to a dramatic rise in interconnect resistivity and concomitant performance degradation [...]
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