HfO₂-based Ferroelectric Field-Effect-Transistor with Large Memory Window and Good Synaptic Behavior

Abstract

In this study, the ferroelectric field-effect-transistor (FeFET) with replacement metal gate process was fabricated. The FeFETs with various gate lengths (LG) and gate widths (WG) were investigated, and large average memory window (MW), up to 2.4 V for various LG and WG, was achieved. The influence of LG on MW was investigated. The experimental results show the MW of FeFET increases with decreasing of LG due to fringe effect. Thus, in the design of FeFET, fringe effect must be considered carefully. The influence of annealing temperature on MW of FeFETs was also investigated. The experimental results show that there are similar MW values for various annealing temperatures due to low density of the interface trap. Furthermore, an artificial electronic synapse based on our FeFETs is demonstrated to mimic synaptic response by applying voltage pulses to their gates. FeFET synapse achieves weight update with small nonlinearity (α p = −0.071, α d = −0.095) and asymmetry (∣α p -α d∣ = 0.166). The influence of LG on synaptic properties was also investigated. Artificial neural network (ANN) simulation based on the electronic synaptic arrays using the hand written digits data sets demonstrates a high recognition accuracy of 95.2%, and the influence of LG on recognition accury of ANN was discussed finally.

Impact of Fringing Field on the Memory Window of FeFET

“…The stronger the fringe electric field, the more ferroelectric domains with larger coercive electric field (E c ) it can flip, leading to an increase in average Ec. As a result, the memory window increases with the increasing of average Ec 5 . For longer gates, the effect of fringing field is less for narrow gate widths, but, with increasing gate widths (W G ), the portion of edge becomes larger with respect to the whole device area.…”

Design and Investigation of a Novel Gate-All-Around Vertical Tunnel FET with Improved DC and Analog/RF Parameters

“…Although SS in F-FET is reported to be relatively lower than 60 mV dec −1 at room temperature, the device could not perform up to the mark in digital circuits due to the presence of hysteresis. 6 In comparison, Tunnel FET is found to be more capable of addressing the issues associated with MOSFET in which the current conduction is based on band-to-band tunneling of charge carriers between valance (conduction) band of source and conduction (valance) band of channel in n-type (p-type) TFET. 7 However, TFETs suffer from a few stumbling blocks, such as low On-state current, inferior analog/RF performance and ambipolar conduction.…”

Significant improvement of endurance of Si FeFET through minor hysteresis loop and narrow write pulse width

“…And the endurance generally remains at 10 4 ∼ 10 6 cycles. 8,10,11,19,21,[23][24][25][26][27][28][29] Recently, high endurance (>10 10 cycles) was reported. Tan et al reported more than 10 10 cycles' endurance by using a thermally grown SiN x interlayer.…”