Hierarchical specification-driven analog fault modeling for efficient fault simulation and diagnosis

Voorakaranam, R.; Chakrabarti, S.; Hou, Junwei; Gomes, Alfred; Cherubal, S.; Chatterjee, Abhijit; Kao, W.H.

doi:10.1109/test.1997.639705

Cited by 49 publications

(15 citation statements)

References 14 publications

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“…In the initialization loop, on average n · Pr{P > s u } (23) samples in the set B 1 will satisfy P > s u and will be placed in the set C 1 . As already mentioned, it is expected that |C 1 | N. In the first iteration of the statistical blockade loop, the number of samples x ∈ A x visited to finally fill in the set B 2 with n samples is on average…”

Section: B Simulation Effort For Generating the Parametric Fault Modelmentioning

confidence: 99%

Fast Monte Carlo-Based Estimation of Analog Parametric Test Metrics

Stratigopoulos

Sunter²

2014

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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International audienceThe accepted approach in industry today to ensure out-going quality in high-volume manufacturing of analog circuits is to directly measure datasheet specifications. To reduce the involved costs it is required to eliminate specification tests or use instead lower-cost alternative tests. However, this is too risky if the resultant fault coverage and yield coverage metrics of the new test approach are not estimated accurately. This paper proposes a methodology to efficiently derive a set of most probable failing and marginally functional circuit instances. Based on this set, we can readily define and estimate fault coverage and yield coverage metrics. Our methodology reduces the required number of Monte Carlo simulations by one or more orders of magnitude. As an illustrative example, the methodology is applied to a radio frequency low-noise amplifier

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Section: B Simulation Effort For Generating the Parametric Fault Modelmentioning

confidence: 99%

Fast Monte Carlo-Based Estimation of Analog Parametric Test Metrics

Stratigopoulos

Sunter²

2014

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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“…Examples of programs that enable these simulations are the combination of ELDO (a mixed-signal simulator marketed by Mentor Graphics ® ) and VHDL-AMS, SABER (a mixed-signal simulator marketed by Analogy Inc.) with its' behavioural language MAST and SMASH with its' behavioural language ABCD. Examples of tools that support hierarchical fault simulation are MiST PROFIT [7], Faultmaxx [8] and GDSFaultsim [9]. Some of these tools combine hierarchical and statistical fault simulation.…”

Section: Closed Loop System Simulationmentioning

confidence: 99%

A fault simulation methodology for MEMS

Rosing

Richardson

Dorey

2000

Proceedings of the Conference on Design, Automation and Test in Europe

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“…Note that, a fault can be differentiated from another fault (or from the fault-free instance) only when the corresponding measurement in the former differs from the latter by a certain minimum threshold. This threshold depends on component tolerances and measurement inaccuracy and is computed by the techniques described in [9]. In this paper, we assume the threshold is given as an input to the test generation program.…”

Section: Test Generation For Analog Circuitsmentioning

confidence: 99%

Partial simulation-driven ATPG for detection and diagnosis of faults in analog circuits

Chakrabarti¹,

Chatterjee²

IEEE/ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE/ACM Digest of Technical Papers (Cat. No.00CH3714

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In this paper, we propose a novel fault-oriented test generation methodology for detection and isolation of faults in analog circuits. Given the description of the circuit-undertest, the proposed test generator computes the optimal transient test stimuli in order to detect and isolate a given set of faults. It also computes the optimal set of test nodes to probe at, and the time instants to make measurements. The test generation program accommodates the effects introduced by component tolerances and measurement inaccuracy, and can be tailored to fit the signal generation capabilities of a hardware tester. Experimental results show that the proposed technique can be applied to generate transient tests for both linear and non-linear analog circuits of moderate complexity in reasonably less CPU time. This will significantly impact the test development costs for an analog circuit and will decrease the time-to-market of a product. Finally, the short duration and the easy-to-apply feature of the test stimuli will lead to significant reduction in production test costs.

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Hierarchical specification-driven analog fault modeling for efficient fault simulation and diagnosis

Cited by 49 publications

References 14 publications

Fast Monte Carlo-Based Estimation of Analog Parametric Test Metrics

Fast Monte Carlo-Based Estimation of Analog Parametric Test Metrics

A fault simulation methodology for MEMS

Partial simulation-driven ATPG for detection and diagnosis of faults in analog circuits

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