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In this paper, we present a novel test generation strategy based on partial numerical fault simulation. Existing fault-based test generation methodologies for analog circuits are based on accurate but expensive fault simulation. In the proposed methodology, fault simulation is terminated before convergence for reasons of simulation speed. The relative fitness of various input stimuli is evaluated based on the results of this partial numerical simulation. A comparison of this new methodology with existing accurate fault simulation based test generation methods, shows up to 15 times speed-up in test generation. IntroductionAlthough there exist fast concurrent and parallel fault simulation algorithms [1,2] and efficient path-based test generation methodologies [3] for digital circuits, fast automatic test generation for analog circuits still poses many barriers that have not been overcome despite intensive research. Analog circuits are typically tested by measuring the circuits specifications. Specification-based testing of analog circuits is expensive and time consuming and the analog and mixed-signal testing community is actively considering the use of fault-based testing similar to that of digital circuits as an alternative. The basic problem with fast fault-based automatic test generation for analog circuits is the lack of fast fault simulation methodologies. Currently, the search for optimum tests during fault-based test generation is performed by invoking existing circuit simulators like HSPICE in a serial manner. Since accurate circuit simulation is CPU-intensive, test generation driven by serial fault simulation (using conventional simulators) is computationally intractable. In this paper, we present a test generation methodology wherein we do not perform accurate fault simulation to drive the search for optimum tests. Instead, we terminate the simulation prior to convergence and evaluate the test stimuli based on the results of partial numerical simulation.Recently, there has been a lot of work in automatic test pattern generation for analog circuits. These test generation schemes can be broadly classified into specification based testing schemes and fault-based testing schemes. In specification-based testing, the performance specifications of the circuit are measured and if any one of them is violated, the circuit under test (CUT) is declared as faulty. Most of the work in specification-based testing has been geared towards eliminating highly correlated tests from a complete set of specification tests [4][5][6][7]. Many other researchers have suggested replacing expensive specification-based tests with low-cost alternate tests [8][9][10][11][12][13].In fault-based testing, functional faults of the CUT are assumed to result from manufacturing and physics-of-failure based defect mechanisms and tests are developed to detect these faults. Defect simulations based on process data are performed on the circuit layout and various defect mechanisms are modeled at the circuit or behavioral level giving a list of pos...

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